Single Metal Layer Semiconductor Substrate for Thin Profile
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Solution Overview
Problem
Current semiconductor package substrates with multiple metal layers are complex and costly to produce, especially as chip sizes decrease, requiring a more efficient and cost-effective solution for mass production with high yield and thin profile.
Innovation Solution
A substrate with a single metal layer, comprising a resin-reinforced core, through openings, a dielectric layer, and a conductive layer, where the conductive layer forms contact pads for electrical connections, reducing thickness and manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple metal layers are used in substrate, then electrical connection capability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple metal layers into a single metal layer, integrating the electrical connection functions that were previously distributed across multiple layers into one unified layer, thereby reducing complexity while maintaining connection capability
Solution Approach 2:
The single metal layer is designed to perform multiple functions simultaneously: providing electrical connections, serving as a ground plane, and enabling signal routing, replacing the specialized functions that were previously distributed across multiple separate metal layers
2Reliability
If multiple metal layers with traces and vias are used, then electrical connection capability is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent merges the functions of multiple metal layers, traces, and vias into a single metal layer structure, eliminating the need for complex multi-layer alignment and via formation processes, thereby simplifying manufacturing
Solution Approach 2:
The patent extracts and eliminates the unnecessary metal layers, traces, and vias from the substrate structure, retaining only the essential single metal layer with contact pads that provides all required electrical connections
3Volume of moving object
If chip package size is decreased, then compactness is improved, but trace and via spacing becomes smaller increasing complexity
Solution Approach 1:
The patent merges multiple connection functions into the single metal layer, eliminating the need for closely spaced vias and traces, allowing compact package design without the complexity of fine-pitch multi-layer routing
Solution Approach 2:
The patent transitions from vertical multi-layer routing to a more planar single-layer configuration with strategically positioned contact pads, changing the dimensional approach to electrical connections and enabling compactness without proportionally increasing routing complexity
Data Source
AI summary
A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.