Single-Metal-Layer Substrate Signal Integrity for High-Speed Semiconductor Packages

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

High-speed semiconductor devices face challenges in maintaining signal integrity due to mismatch budgets in multi-layered substrates, where metal-filled vias introduce dimensional mismatches and electrical impedance discontinuities, leading to phase angle mismatches and increased costs.

Innovation Solution

A single-metal-layer substrate is used with patterned contact and stitch pads, where differential pairs are placed in close proximity with a grounded trace and wire bond in between to minimize crosstalk, and depopulating contact pads to accommodate stitch pads, ensuring matched length and parallelism of bonding wires.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multi-layered substrates with metal-filled vias are used, then routing flexibility is improved, but manufacturing precision deteriorates due to dimensional mismatches and impedance discontinuities

Engineering Contradiction:

Improverouting flexibilityVSAvoidsignal path dimensional mismatch

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent removes the via holes and multiple metal layers from the substrate structure, extracting the problematic elements that caused manufacturing precision deterioration. The solution uses a single-metal-layer substrate without vias, eliminating the source of dimensional mismatches and impedance discontinuities while maintaining routing capability through the single layer

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of using multiple metal layers with vias to achieve routing flexibility, the patent inverts the approach by using a single metal layer with an optimized pad array configuration. The routing is achieved through careful placement of contact pads and stitch pads on the single layer, eliminating the need for vertical via connections

Inventive Principle:

Principle #13The other way round (Inversion)

2Adaptability or versatility

If multi-layered substrates with metal-filled vias are used, then routing flexibility is improved, but device complexity increases

Engineering Contradiction:

Improverouting flexibilityVSAvoidsubstrate structure complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes the complex multi-layered structure with vias, simplifying the substrate to a single metal layer. This reduction eliminates the complexity of stacking multiple layers and forming vias through them, while the routing functionality is maintained through optimized two-dimensional pad placement

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the substrate into distinct functional zones with different pad configurations - contact pads for solder bumps and stitch pads for wire bonding. This segmentation allows each zone to be optimized for its specific function while maintaining overall routing flexibility without requiring complex multi-layer structures

Inventive Principle:

Principle #1Segmentation

3Reliability

If differential pairs are placed in close proximity to minimize crosstalk, then signal integrity is improved, but manufacturing precision deteriorates due to spacing constraints

Engineering Contradiction:

Improvesignal integrityVSAvoidpad placement precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent introduces a grounded trace as an intermediary element between adjacent differential pairs. This ground trace acts as a shield that reduces electromagnetic coupling between pairs, allowing them to be placed in close proximity without excessive crosstalk. The intermediary ground plane enables tighter spacing while maintaining signal integrity

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent uses grounded traces and wire bonds to create equipotential reference planes between differential pairs. By establishing a common ground potential between adjacent signal pairs, the voltage difference and resulting electromagnetic interference are reduced, enabling closer placement while maintaining signal integrity

Inventive Principle:

Principle #12Equipotentiality

Data Source

PatentUS8723337B2Structure for high-speed signal integrity in semiconductor package with single-metal-layer substrate

Publication Date: 2014.05.13 TEXAS INSTRUMENTS INC

AI summary

A semiconductor chip (101) with bond pads (110) on a substrate (103) with rows and columns of regularly pitched metal contact pads (131). A zone comprises a first pair (131a, 131b) and a parallel second pair (131c, 131d) of contact pads, and a single contact pad (131e) for ground potential; staggered pairs of stitch pads (133) connected to respective pairs of adjacent contact pads by parallel and equal-length traces (132a, 132b, etc.). Parallel and equal-length bonding wires (120a, 120b, etc.) connect bond pad pairs to stitch pad pairs, forming differential pairs of parallel and equal-length conductor lines. Two differential pairs in parallel and symmetrical position form a transmitter/receiver cell for conducting high-frequency signals.