Single-MOSFET Charge Multiplier for Low-Transistor Neural Computing
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Solution Overview
Problem
Machine learning applications, particularly neural networks, require large numbers of transistors for digital multiplication, leading to increased complexity and time consumption, despite efforts to improve throughput with parallel processing and systolic architectures.
Innovation Solution
A multiplier circuit utilizing a MOSFET in common source configuration with proportional current sources and capacitors to reduce the number of transistors, enabling efficient multiplication with a smaller transistor count and optimized depleted junction structures to minimize overlap capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If digital multipliers are implemented using conventional transistor-based logic gates, then multiplication functionality is achieved, but the transistor count becomes large and circuit complexity increases
Solution Approach 1:
The patent replaces conventional digital logic gate systems with an analog charge-based multiplication system. Instead of using multiple transistors arranged in logic gates to perform bitwise multiplication, the invention uses a single transistor as a switch controlled by voltage inputs, where multiplication is achieved through charge accumulation on capacitors. This substitution of the mechanical/digital system with an analog charge-based system dramatically reduces transistor count from dozens to just one, directly resolving the contradiction between device complexity and functional reliability.
Solution Approach 2:
The patent changes the operating parameters from digital voltage levels representing binary states to analog voltage and charge values that directly represent numerical magnitudes. By using continuous voltage ranges (e.g., 0-1V representing 0-1000) and charge quantities proportional to these voltages, the system performs multiplication through physical charge accumulation rather than sequential logic operations. This parameter change enables accurate multiplication with minimal transistors, resolving the contradiction between simplicity and accuracy.
2Productivity
If multiple parallel threads and systolic architectures are used to improve throughput, then multiplication speed increases, but the number of transistors and architectural overhead increases
Solution Approach 1:
The patent creates a universal multiplication circuit that can handle any multiplication operation using a single standardized configuration. The same single-transistor circuit can multiply any two voltage-represented numbers by simply changing the input voltages, without requiring reconfiguration or additional hardware. This multi-functionality eliminates the need for multiple parallel threads and complex systolic architectures, achieving high throughput with minimal overhead by making one circuit do everything.
Solution Approach 2:
The patent enables continuous multiplication operations by maintaining charge on capacitors and using voltage levels that can be continuously adjusted. Unlike digital systems that require discrete cycles for loading, computing, and clearing, this analog system can continuously accept new voltage inputs and produce proportional charge outputs, achieving sustained high throughput without the overhead of parallel processing architectures.
3Loss of time
If conventional digital multiplication is used, then accurate results are obtained, but the operation time spans several cycles increasing latency
Solution Approach 1:
The patent performs preliminary action by pre-charging capacitors to represent input values before the multiplication operation begins. The input voltages are converted to proportional charges on capacitors in advance, so that when the multiplication is triggered, the result is immediately available as the product of these pre-prepared charge values. This eliminates the need for multi-cycle computation and reduces latency to a single operational cycle.
Solution Approach 2:
The patent replaces multi-cycle digital computation with a single-cycle analog charge multiplication process. Instead of sequentially processing bits through multiple logic gate cycles, the system uses the physical property that charge accumulation is proportional to the product of input voltages, achieving accurate multiplication in one operational cycle and dramatically reducing latency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves reduced transistor count and faster multiplication operations, improving throughput and reducing noise and power consumption, while maintaining accuracy through correlated double sampling and direct charge handling.
Implementation Method 1
A first capacitor has a first terminal coupled to a first I1 of the two currents and a gate of the MOSFET
Implementation Method 2
A MOSFET in a common source configuration is used as a comparator correlated to a Vt comparator threshold
Data Source
AI summary
A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to a drain terminal of the MOSFET. An inverter has an input coupled to the drain terminal of the MOSFET. An output of the inverter gates two currents whose current magnitudes are proportional. A first capacitor has a first terminal coupled to a first of the two currents and a gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to a second of the two currents and a second terminal coupled to the first of the two currents. The multiplier is first reset by discharging a gate capacitance of the MOSFET and then allowing it to be recharged to a Vt comparator threshold after which a charge is removed from the gate terminal of the MOSFET reducing a voltage on the gate terminal below the Vt comparator threshold, causing the two currents to be enabled until the Vt comparator threshold reaches a previous Vt comparator threshold and the inverter turns off the two currents. In a next reset phase, the second capacitor holds a multiplied value of charge.