Single NMOS Charge Pump Passgate for DRAM Efficiency
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Solution Overview
Problem
Conventional charge pumps in semiconductor devices, used in DRAM and other applications, face inefficiencies due to the use of PMOS and NMOS transistors in series as passgates, which limits charge transfer efficiency and increases layout area.
Innovation Solution
Implementing a charge pump unit core with a single NMOS transistor as the passgate, allowing for modified clock phase timing and control of bulk voltage to enhance efficiency and reduce layout area, eliminating the impact of threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PMOS and NMOS transistors are arranged in series as passgates, then charge transfer can be achieved, but layout area increases and charge transfer efficiency decreases
Solution Approach 1:
The patent extracts and removes the PMOS transistor from the conventional series arrangement of PMOS and NMOS passgates. By using only the NMOS transistor as the passgate, the design eliminates the redundant component while maintaining charge transfer functionality, thereby reducing layout area and improving charge transfer efficiency.
Solution Approach 2:
The patent introduces a bulk voltage generation mechanism as an intermediary control system. By independently controlling the bulk voltage of the NMOS passgate, the design compensates for the threshold voltage effect and enables efficient charge transfer without requiring the additional PMOS transistor, thus resolving the contradiction between simplicity and performance.
2Productivity
If PMOS and NMOS transistors are arranged in series as passgates, then charge transfer functionality is maintained, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the PMOS transistor from the passgate structure, retaining only the NMOS transistor. This simplification reduces device complexity while maintaining charge transfer functionality through optimized bulk voltage control and clock phase timing.
Solution Approach 2:
The patent changes the operational parameters by independently controlling the bulk voltage of the NMOS passgate and adjusting clock phase timing. This parameter optimization allows the simplified single-transistor structure to achieve the same charge transfer capability as the conventional two-transistor series arrangement.
3Productivity
If conventional series passgate structure is used, then charge transfer is achieved, but current efficiency and power efficiency are reduced
Solution Approach 1:
By removing the PMOS transistor from the series passgate configuration, the patent reduces the number of active components that consume power during charge transfer operations. The simplified NMOS-only structure decreases static and dynamic power consumption while improving current efficiency.
Solution Approach 2:
The patent implements self-service through automated bulk voltage control that adapts to operational conditions. The bulk voltage generation circuit automatically adjusts to maintain optimal NMOS passgate performance, enabling efficient charge transfer without requiring additional control circuits that would increase power consumption.
Data Source
AI summary
Apparatus and methods that have a semiconductor charge pump can be implemented in a variety of applications. Such a charge pump can have a charge pump unit core that includes a pump section and a single passgate coupled to the pump section to transfer charge, where the single passgate is a n-channel metal-oxide semiconductor (NMOS) transistor coupled directly to an input and an output of the charge pump unit core. The transfer of charge can be based on a set of clock signals. Additional apparatus, systems, and methods are disclosed.