Single-Node Bus Memory With Active Drivers
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Solution Overview
Problem
Integrated circuit devices require additional memory with a minimal number of connections, as they become smaller and fewer input-output signal connections are used for cost and space considerations, while existing memory systems often require multiple pins for memory address selection and operation.
Innovation Solution
A digital system utilizing a single-node data, address, and control bus with active pull-up and pull-down bus drivers, allowing for a memory array to be coupled to a digital processor with a minimum number of connections, such as a three-pin integrated circuit package, and enabling memory address selection through programming via the single-node bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory is connected to a digital processor with multiple pins for address selection and operation, then the memory operation reliability is improved, but the number of connections increases
Solution Approach 1:
The patent combines data, address, and control signals into a single bidirectional bus for communication between the microcontroller and memory. This merging of multiple signal types into one shared communication channel reduces the number of required connections from multiple pins to just three pins (VDD, GND, and the single-node bus), while maintaining reliable memory operation through protocol-based signal differentiation
Solution Approach 2:
The single-node bus serves multiple functions by carrying data, address, and control signals sequentially. The bus is used for writing commands to the memory, reading data from the memory, and exchanging acknowledgment signals, making it a universal communication interface that replaces multiple dedicated signal lines
2Device complexity
If integrated circuit devices use fewer input-output signal connections, then cost and space are reduced, but the memory integration capability is limited
Solution Approach 1:
The system dynamically switches the role of the single-node bus between different signal types (data, address, control) based on the operation phase. The microcontroller and memory dynamically coordinate their communication protocol to ensure proper signal interpretation, allowing the same physical connection to adapt to different functional requirements without additional pins
Solution Approach 2:
A communication protocol acts as an intermediary layer between the physical single-node bus and the memory operations. This protocol mediates the translation of high-level memory operations into sequential signal exchanges on the single bus, enabling complex memory integration capabilities despite the simple physical connection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables reliable transmission protocols and minimizes the number of connections required, allowing for efficient memory operation in low pin count integrated circuit packages, enhancing memory integration with digital devices while maintaining reliable data transfer.
Implementation Method 1
an active pull-up and pull-down bus driver for driving the single-node data, address and control bus
Implementation Method 2
an active pull-up and pull-down bus driver for driving the single-node data, address and control bus
Data Source
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Figure 3
Figure 4~5
AI summary
An integrated circuit digital device is coupled to a memory with a single-node data, address and control bus. The memory may be a non-volatile memory and/or volatile memory. The memory may be packaged in a low pin count integrated circuit package. The memory integrated circuit package may have a ground terminal, VSS; a power terminal, VDD or VCC; and a bidirectional serial input-output (I/O) terminal, SCIO. Memory block address set-up may be performed via software instructions through the SCIO terminal. In addition, hardwired memory block address selection terminals A0 and A1 may be used when more then three terminals are available on the memory integrated circuit package. The memory may have active pull-up and pull-down drivers coupled to the single-node data, address and control bus.