Single Page Buffer Structure for Flash Memory Operations
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Solution Overview
Problem
Conventional flash memory devices require separate page buffer circuits for multi-bit programming, cache program operations, and page copy-back operations, leading to increased costs due to the need for distinct structures for each function.
Innovation Solution
A flash memory device with a single page buffer structure capable of performing multi-bit program and read operations, cache program operations, and page copy-back operations, utilizing a sense node connected to a selected bit line, a load circuit for pre-charging, and multiple sense and register circuits to store data values based on voltage levels, along with PMOS and NMOS transistors for control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate page buffer circuits are used for multi-bit programming, cache program operations, and page copy-back operations, then each operation can be performed with dedicated circuitry, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements a universal page buffer circuit that can perform multiple functions (multi-bit programming, cache program operations, and page copy-back operations) using a single integrated structure. The page buffer includes a sense amplifier unit, a first register unit, and a second register unit that can be configured through control signals to execute different operations, eliminating the need for separate dedicated circuits for each function.
2Ease of manufacture
If separate page buffer circuits are used for different operations, then each operation has optimized circuitry, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple previously separate page buffer circuits into a single integrated page buffer structure. The sense amplifier unit, first register unit, and second register unit are combined and controlled through control signals to perform different operations, reducing the total number of circuits needed and lowering manufacturing cost while maintaining versatility.
3Device complexity
If a single page buffer structure is used for all operations, then device complexity and cost are reduced, but operational flexibility may be compromised
Solution Approach 1:
The patent implements a dynamic control mechanism where control signals can configure the single page buffer structure to perform different operations. The sense amplifier unit and register units can be dynamically activated or deactivated based on the required operation (multi-bit programming, cache program, or page copy-back), providing operational flexibility without requiring separate dedicated circuits for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient management of memory operations using a single page buffer structure, reducing the need for separate memory devices and lowering costs while maintaining performance across various operations.
Implementation Method 1
a load circuit connected to the sense node and adapted to pre-charge the sense node
Implementation Method 2
a first sense and register circuit connected to the sense node and adapted to store a first data value in accordance with a first voltage level of the sense node
Data Source
AI summary
A flash memory device is provided, and the flash memory device comprises memory cells, a sense node connected to a selected bit line, a load circuit connected to the sense node, and first and second sense and register circuits, each connected to the sense node. The first sense and register circuit is configured to store a first data value in accordance with the voltage level of the sense node during an initial read interval of a multi-bit program operation. The load circuit is configured to selectively pre-charge the sense node in accordance with the data value stored in the first sense and register circuit during a verify read interval of the multi-bit program operation. A multi-bit programming method for the flash memory device is also provided.