Single-Pass Compilation for Dynamically Reconfigurable Logic Blocks
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Solution Overview
Problem
Existing electronic design automation (EDA) tools fail to achieve proper timing closure for dynamically reconfigurable logic blocks, as they only consider initial configurations during timing analysis, leading to incomplete timing analysis and suboptimal placement and routing solutions.
Innovation Solution
A method for generating a timing netlist that accounts for timing delays and relationships of both base and target configurations of dynamically reconfigurable logic blocks, allowing for comprehensive timing constraints to be reflected during a single hardware description language (HDL) compilation, thereby enabling precise timing closure and reducing development time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If EDA tools only consider initial configuration during timing analysis, then the compilation process is simpler and faster, but timing closure is incomplete and placement/routing solutions are suboptimal
Solution Approach 1:
The patent applies preliminary action by performing timing analysis for all configurations (base and target) during the initial compilation pass, rather than waiting for subsequent reconfiguration steps. The system generates timing constraints and performs timing closure for multiple configurations upfront, ensuring that placement and routing solutions are optimized for all possible states of the dynamically reconfigurable logic blocks before the design is deployed.
2Reliability
If EDA tools perform timing analysis for all configurations, then timing closure accuracy improves, but the compilation process becomes more complex and time-consuming
Solution Approach 1:
The patent applies universality by creating a unified timing analysis framework that handles both base and target configurations within a single compilation pass. The system generates a comprehensive timing constraint model that universally applies to all configurations of dynamically reconfigurable logic blocks, allowing the same compilation process to serve multiple configuration scenarios simultaneously rather than requiring separate analysis passes for each configuration.
3Reliability
If multiple compilation passes are performed for different configurations, then timing constraints are more accurate, but development time increases
Solution Approach 1:
The patent applies merging by combining the timing analysis for base and target configurations into a single integrated compilation pass. The system merges multiple timing constraint sets into one comprehensive timing analysis, performing synthesis, placement, and routing optimization for all configurations simultaneously. This eliminates the need for sequential compilation passes, thereby maintaining accurate timing constraints while improving design throughput.
4Reliability
If timing constraints are over-constrained to account for all configurations, then timing closure reliability improves, but the compilation becomes more difficult and time-consuming
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting timing constraint parameters based on the specific configuration being analyzed. The system modifies timing parameters such as clock periods, setup/hold times, and delay values according to the operational state of dynamically reconfigurable logic blocks. This allows the compilation process to apply appropriate timing constraints for each configuration without over-constraining the overall design, thereby maintaining reliability while reducing compilation time.
Data Source
AI summary
A method for designing a system on a target device includes generating a timing netlist that reflects timing delays and timing relationships of a base configuration of a block in the system and a target configuration of the block in the system, wherein the base configuration of the block and the target configuration of the block implement different functionalities, and performing synthesis, placement, and routing on the system in response to the timing netlist.