Single Patterning Process for Oxide Thin Film Transistors
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Solution Overview
Problem
The fabrication process of oxide thin film transistors requires six patterning processes, leading to unstable performance, long fabrication cycles, and increased costs.
Innovation Solution
A method for forming active layers, source electrodes, and drain electrodes of thin film transistors using a single patterning process, which includes coating a photoresist, exposing and developing with a dual-tone mask, and etching to create the necessary transistor structures, thereby reducing the number of fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If six patterning processes are used to form gate line, gate electrode, gate insulating layer, active layer, etching barrier layer, source electrode, drain electrode, passivation layer and via hole, then the transistor structure can be formed, but the fabrication cycle becomes long and fabrication cost increases
Solution Approach 1:
The patent combines multiple patterning processes into a single patterning step by using a multi-layer structure where the gate line, gate electrode, active layer, source electrode, and drain electrode are formed simultaneously. This merging of processes directly reduces the fabrication cycle while maintaining the required structural precision through the integrated design of the multi-layer system.
Solution Approach 2:
The single patterning process serves multiple functions by simultaneously defining the gate line, gate electrode, active layer, source electrode, and drain electrode. This multi-functional approach eliminates the need for separate patterning steps for each component, thereby shortening the fabrication cycle without compromising manufacturing precision.
2Manufacturing precision
If six patterning processes are used to form transistor components, then the transistor structure can be formed, but the fabrication cost increases
Solution Approach 1:
By merging six separate patterning processes into one integrated patterning step, the patent reduces the number of process steps, material consumptions, and equipment usage fees. This directly lowers fabrication cost while the multi-layer design ensures that manufacturing precision is maintained through unified process control.
Solution Approach 2:
The single patterning process performs multiple functions simultaneously, reducing the overall process complexity and fabrication cost. The multi-layer structure enables this universal approach by allowing one patterning step to define multiple transistor components, thereby simplifying manufacturing and reducing costs.
3Manufacturing precision
If six patterning processes are used to form transistor components, then the transistor structure can be formed, but the performance becomes unstable
Solution Approach 1:
The integration of multiple patterning processes into a single step reduces the number of interface points between processes, thereby minimizing cumulative errors and variations. This unified approach enhances performance stability by ensuring consistent alignment and dimensional control across all transistor components formed in the single patterning process.
Solution Approach 2:
The single patterning process with multi-functional capability ensures uniform process conditions across all transistor components, reducing variability and improving performance stability. By forming all critical components in one step, the patent eliminates the performance instability that arises from multiple sequential patterning processes with varying conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly shortens the fabrication period, improves transistor performance, enhances stability, and increases yield, making the transistors more suitable for high-frequency and high-resolution displays.
Implementation Method 1
exposing and developing by using a dual-tone mask, wherein a connection region of the drain electrode of the first thin film transistor and the gate electrode of the second thin film transistor, regions of the data line and the power line, and regions of the source electrodes and the drain electrodes of the first thin film transistor and the second thin film transistor are photoresist-completely-reserved regions, a first channel region of the first thin film transistor and a second channel region of the second thin film transistor are photoresist-partially-reserved regions, and regions other than the above regions are photoresist-completely-removed regions
Implementation Method 2
removing the source-drain metal layer and the active layer film corresponding to the photoresist-completely-removed regions by a first etching process
Data Source
AI summary
A display device, an array substrate and a fabrication method thereof are provided. The array substrate comprises a data line and a gate line, the data line and the gate line intersect with each other to define a pixel region. The pixel region comprises a first thin film transistor and a pixel electrode. The fabrication method comprises: forming an active layer film and a source-drain metal layer on a substrate, and forming an active layer, a source electrode and a drain electrode of the first thin film transistor on the substrate by a single patterning process.