Single-Phase Clock Duty Cycle Correction Using Internal Lock Detection
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Solution Overview
Problem
Conventional duty cycle correction circuits are limited in correcting the duty cycle of single-phase clock signals, which are advantageous in terms of power consumption but lack the opposite phase necessary for effective duty cycle correction, leading to difficulties in precise timing for semiconductor circuits.
Innovation Solution
A duty cycle correction circuit that generates a locking signal using an internal clock signal to correct the duty cycle of a single-phase external clock signal, incorporating a correction circuit and a locking signal detection circuit to calibrate the duty cycle, enabling precise correction even with single-phase signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If differential clock signals are used for duty cycle correction, then duty cycle correction is easy to implement, but power consumption increases
Solution Approach 1:
The patent generates a pseudo-differential signal by copying and inverting the single-phase clock signal through buffer circuits. This allows the duty cycle correction circuit to operate using differential signaling principles while the actual clock input remains single-phase, thus maintaining power efficiency while enabling effective duty cycle correction
Solution Approach 2:
The patent separates the clock signal processing into distinct functional blocks: a buffer circuit that generates the inverted signal, and a duty cycle correction circuit that processes the differential pair. This segmentation allows the power-consuming differential processing to occur only on generated signals rather than the original clock, reducing overall power consumption
2Use of energy by moving object
If single-phase clock signal is used to reduce power consumption, then power consumption decreases, but duty cycle correction becomes difficult
Solution Approach 1:
The patent introduces an intermediary buffer circuit that converts the single-phase clock signal into a differential pair. This intermediary component enables the duty cycle correction circuit to receive differential signals for easy correction while the external interface remains single-phase, thus maintaining power efficiency while enabling effective duty cycle correction
3Device complexity
If duty cycle correction is not performed, then circuit complexity is reduced, but timing accuracy deteriorates
Solution Approach 1:
The patent employs a feedback mechanism where the duty cycle correction circuit continuously monitors the differential clock signals and adjusts the phase and duty cycle to maintain optimal timing. The locking signal detection circuit provides feedback to ensure the correction remains accurate, thus maintaining timing precision without requiring overly complex circuitry
Data Source
AI summary
A duty cycle correction circuit is provided. The duty cycle correction circuit may include a correction circuit configured to correct a duty cycle of an external clock signal according to a locking signal. The duty cycle correction circuit may include a locking signal detection circuit configured to generate the locking signal for correcting the duty cycle of the external clock signal, using an internal clock signal generated in a semiconductor circuit.