Single-Phase Clock-Gating Circuit for Lower Leakage and Power
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Solution Overview
Problem
The increasing complexity and number of devices in current integrated circuits (ICs) lead to significant power consumption, with active and leakage power being major contributors, posing a challenge in prolonging battery life of mobile devices like laptops and mobile phones.
Innovation Solution
A single-phase clock-gating circuit design utilizing specific configurations of PMOS and NMOS transistors, NOR gates, NAND gates, and inverters, which reduces the number of transistors and clock pin capacitance, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional multi-phase clock-gating circuits are used, then clock control functionality is achieved, but transistor count and circuit complexity increase
Solution Approach 1:
The patent merges multiple clock phases into a single-phase architecture by combining the functionality of multiple clock-gating circuits into one unified circuit. This consolidation reduces the total transistor count while maintaining the essential clock control functionality through shared transistors and integrated logic paths.
Solution Approach 2:
The single-phase clock-gating circuit achieves multi-functionality by using a shared set of transistors to control multiple clock outputs simultaneously. The circuit can generate different clock phases and control signals from a single input clock, making the circuit versatile while reducing overall complexity.
2Reliability
If more transistors are used in clock-gating circuits, then clock control capability is enhanced, but power consumption increases
Solution Approach 1:
By merging multiple clock-gating functions into a single-phase circuit with shared transistors, the patent reduces the total number of active devices. Fewer transistors mean lower dynamic power consumption while maintaining adequate clock control capability for the intended application.
Solution Approach 2:
The patent extracts and eliminates redundant transistors and circuit elements from conventional multi-phase designs. By removing unnecessary components while retaining essential clock control functionality, the circuit achieves lower power consumption without significantly compromising control capability.
3Ease of operation
If conventional clock-gating circuits are used, then clock signal distribution is achieved, but leakage current is high
Solution Approach 1:
The single-phase architecture merges clock signal distribution paths to share common transistors and control logic. This consolidation reduces the number of transistor switches that can exhibit leakage, thereby reducing total leakage current while maintaining effective clock distribution to multiple outputs.
Solution Approach 2:
The patent removes redundant transistor switches and control paths from conventional designs. By eliminating unnecessary switching elements that contribute to leakage current, the circuit achieves lower static power consumption while preserving clock signal distribution functionality.
4Use of energy by moving object
If transistor count is reduced in clock-gating circuits, then power consumption decreases, but circuit functionality may be compromised
Solution Approach 1:
The patent combines multiple clock-gating functions into a single-phase circuit that uses fewer transistors. By intelligently sharing transistors across multiple control paths and using efficient logic synthesis, the circuit maintains adequate functionality for clock distribution while achieving lower power consumption.
Solution Approach 2:
The single-phase circuit implements partial clock control functionality compared to full multi-phase designs, focusing on the essential clock distribution needs. This selective implementation achieves acceptable functionality with significantly reduced transistor count and power consumption for applications that don't require all possible clock control features.
Data Source
AI summary
A circuit includes three PMOS transistors (PMOS) and three NMOS transistors (NMOS). The first PMOS has a source receiving a supply voltage and a gate receiving a first signal. The second PMOS has a source coupled to a drain of the first PMOS, a gate receiving a clock signal, and a drain generating a second signal. The third PMOS has a source receiving the supply voltage, and a drain coupled to the drain of the second PMOS. The first NMOS has a drain coupled to the drain of the second PMOS, and a gate coupled to a gate of the third PMOS. The second NMOS has a gate receiving the first signal, and a drain coupled to a source of the first NMOS. The third NMOS has a gate coupled to the gate of the third PMOS transistor, and a drain coupled to the drain of the third PMOS.