Single-Phase Clocked Flip-Flop for Low Leakage Data Retention
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Solution Overview
Problem
Existing flip-flop circuits face challenges in reducing power consumption, particularly due to the need for additional clock inverters and higher clock-to-Q delay in dynamic designs without active storage elements.
Innovation Solution
A single-phase clock-based flip-flop design that uses a single clock signal for both primary and secondary latches, allowing data to be retained as long as the power supply is available and conserving power by disconnecting paths to power or ground based on stored data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dynamic design without active storage elements is used, then power consumption is reduced, but clock-to-Q delay increases
Solution Approach 1:
The flip-flop is divided into two separate latches (first latch and second latch) that operate on different clock phases. The first latch captures data on the rising edge of the clock signal, while the second latch transfers data to the output on the falling edge. This segmentation allows each latch to be optimized for low power consumption while maintaining proper timing relationships, thereby reducing overall power consumption without significantly increasing clock-to-Q delay.
Solution Approach 2:
The circuit uses periodic clocking with two distinct phases (rising edge and falling edge) to control data flow through the latches. By synchronizing latch operations with periodic clock edges, the design achieves low power consumption through controlled switching only at necessary moments, while maintaining predictable timing and acceptable clock-to-Q delay performance.
2Reliability
If additional clock inverters are added, then clock signal distribution is improved, but power consumption increases
Solution Approach 1:
The design merges the clocking function into the latch structure itself, where the latches are directly clocked by the main clock signal without requiring separate inverter stages. This integration eliminates redundant clock inversion operations and reduces the number of active components in the clock distribution path, thereby improving reliability while reducing power consumption.
Solution Approach 2:
The design extracts and eliminates unnecessary clock inverters from the traditional flip-flop architecture. By using latches that can be directly controlled by the clock signal edges, the circuit removes the need for additional inverter stages, reducing both power consumption and component count while maintaining proper clock signal distribution to the storage elements.
Data Source
AI summary
Embodiments herein relate to a flip-flop circuit which uses a single clock signal for both the primary and secondary latches with either a “0” or a “1” being used to write into the primary latch and either a “1” or a “0,” respectively, being used to write into the secondary latch. The flip-flop can retain the data as long as the power supply is available. Additionally, the flip-flop conserves power by disconnecting one or more paths to power or ground automatically based upon the data that is being stored, thus reducing the leakage current during a storage mode of operation.