Single-Phase Differential Flip-Flop Without Precharge or Feedback
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Solution Overview
Problem
Existing flip-flop designs face challenges in high-speed operation due to issues like slow transitions, skew, and race conditions, especially at low clock frequencies and high temperatures, and require multiple clock phases, which complicates clock distribution and leads to inefficiencies.
Innovation Solution
A single-phase flip-flop circuit design that includes cross-coupled PMOS and NMOS connected via a pass gate, operating with a single-phase clock, eliminating direct feedback and precharged states, and incorporating both static and dynamic properties to enhance speed and reduce area density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static flip-flop design with two inverter-based latches is used, then reliability is improved, but area and delay increase
Solution Approach 1:
The patent extracts the clock inversion requirement from the flip-flop design by using separate clock inputs for the master and slave latches. This eliminates the need for one of the two inverter-based latches, reducing area and delay while maintaining reliability through the cross-coupled NMOS feedback path.
Solution Approach 2:
The patent merges the clock signal distribution by using a single clock input that directly controls both master and slave latches without requiring a separate inverted clock signal. This consolidation reduces the number of components and simplifies the overall circuit architecture.
2Speed
If dynamic logic flip-flop is used, then operating speed and area density are improved, but clock tree synthesis becomes challenging
Solution Approach 1:
The patent removes the requirement for clock signal inversion by using separate clock inputs (CLK for master, CK for slave) that can be independently controlled. This extraction of the inversion requirement simplifies clock tree synthesis while maintaining high operating speed through dynamic logic operation.
Solution Approach 2:
The patent employs dynamic logic with precharge and evaluate phases, allowing the flip-flop to operate at high speeds. The dynamic nature of the logic gates enables faster switching compared to static logic, while the separate clock inputs provide flexibility in timing control.
3Speed
If cross-coupled PMOS and NMOS with pass gate is used, then speed and area density are improved, but direct feedback and precharged state must be eliminated
Solution Approach 1:
The patent removes the direct feedback path from the output of the cross-coupled NMOS to the input, instead using the clock signals to control the master and slave latches. This eliminates the need for precharged states while maintaining high speed operation through the dynamic logic structure.
Solution Approach 2:
The patent introduces clock signals as intermediaries that control the master and slave latches, replacing the need for direct feedback and precharged states. The clock signals mediate the data transfer between stages, simplifying the circuit structure while maintaining high performance.
Data Source
AI summary
The present disclosure relates to a high speed, differential input, single phase clock circuit. The circuit may include a cross-coupled PMOS connected with a cross-coupled NMOS via a pass gate. The circuit may further include a single-phase clock in communication with the cross-coupled PMOS and the cross-coupled NMOS. The circuit may also include a master and a slave each having an output node that charges and discharges to VDD or ground respectively, wherein there is no direct feedback from an output of the circuit to an input the circuit and there is no precharged state in the circuit.