Single-Phase MUX-D Flip-Flop for Lower Clock Power
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Solution Overview
Problem
Existing flipflop designs face challenges in improving Power Performance Area (PPA) due to high dynamic power consumption and sequential overhead, particularly in clock power and area efficiency.
Innovation Solution
A single-phase clocked data multiplexer (MUX-D) scan capable flipflop design is introduced, featuring a complementary metal oxide semiconductor (CMOS) NAND structure that eliminates clock inversions and maximally shares n-type devices across NAND structures, replacing traditional master-slave topology with an all-CMOS NAND, And-OR-Inverter logic to enhance power and performance while minimizing poly-breaks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional master-slave flipflop topology with transmission gates and clock inversions is used, then flipflop functionality is achieved, but dynamic power consumption and area increase
Solution Approach 1:
The patent removes clock inversion stages from the traditional master-slave flipflop architecture. By extracting the inversion function and eliminating redundant clock phases, the design reduces dynamic power consumption associated with charging and discharging clock-related capacitances while maintaining edge-triggered functionality through a single clock phase.
Solution Approach 2:
The patent merges multiple n-type devices across NAND structures to share common transistors. This consolidation reduces the total device count and interconnect capacitance, thereby lowering dynamic power consumption while preserving the flipflop's storage and timing functionality.
2Area of stationary object
If traditional master-slave flipflop topology with transmission gates is used, then flipflop functionality is achieved, but area efficiency decreases
Solution Approach 1:
The patent combines multiple n-type devices into shared transistors across NAND structures. This merging reduces the total transistor count and minimizes poly-breaks (discontinuous polysilicon regions), leading to compact layout and improved area efficiency while maintaining functional complexity.
Solution Approach 2:
The shared n-type devices serve multiple functions simultaneously - they participate in multiple NAND gate operations and clock distribution paths. This multi-functionality reduces the overall device count required, thereby decreasing the flipflop's area footprint.
3Loss of time
If clock inversions are used in flipflop design, then proper clock phasing is achieved, but sequential overhead increases
Solution Approach 1:
The patent extracts and removes the clock inversion stages from the circuit. By eliminating these inverter stages, the design reduces the clock-to-Q delay and setup time requirements, thereby decreasing sequential overhead while still achieving proper edge-triggered operation through the single-phase clocking scheme.
Data Source
AI summary
A single-phase clocked data multiplexer (MUX-D) scan capable flipflop (FF) design that improves over existing transmission-gate (t-gate) based master-slave flipflops in terms of dynamic capacitance (Cdyn) as well as performance while remaining comparable in area. Unique features of the design are a complementary metal oxide semiconductor (non-t-gate) style structure with an improvement in circuit parameters achieved by eliminating clock inversions and maximally sharing NMOS devices across NAND structures. The core of the flipflop adopts an all CMOS NAND, And-OR-Inverter (AOI) complex logic structure to implement a true edge-triggered flip-flop functionality.