Single-Pin Timing Capacitor Monitoring for Synchronized Parallel ICs
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Solution Overview
Problem
When multiple IC chips are coupled in parallel, they often lose synchronization due to variations in semiconductor processing, causing issues like incorrect system behavior and potential damage, as they do not simultaneously recognize the end of a timing period.
Innovation Solution
Implementing a dual-threshold monitoring system where IC chips detect both a rising and a falling threshold voltage on an external capacitor, with the rising threshold set below the voltage threshold minus a maximum random offset, allowing all chips to remain synchronized by enabling detection of the falling threshold only after reaching the rising threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single voltage threshold is used for timing, then the timing circuit is simple, but IC chips lose synchronization due to processing variations
Solution Approach 1:
The single voltage threshold is segmented into two distinct thresholds: a rising threshold (e.g., 2.5V) and a falling threshold (e.g., 1.5V). This segmentation allows the timing circuit to detect both the start and end of the timing period reliably, compensating for processing variations across different IC chips while maintaining circuit simplicity.
Solution Approach 2:
Instead of detecting only the rising edge at a single threshold, the circuit detects both rising and falling edges using inverted threshold levels. The falling threshold is set below the rising threshold, creating a hysteresis effect that ensures all chips synchronize at the same physical voltage point regardless of individual threshold variations.
2Power
If multiple IC chips are coupled in parallel to increase current capability, then the system power delivery is improved, but synchronization is lost due to threshold variations
Solution Approach 1:
All IC chips in the parallel configuration share a common external capacitor and monitor the same voltage node. The dual-threshold mechanism ensures that despite individual chip variations, all chips experience the same effective timing voltage levels, creating an equipotential timing reference that maintains synchronization across all parallel chips.
3Measurement precision
If the rising threshold is set close to the voltage threshold, then timing precision is improved, but chips may fail to detect the falling threshold due to random offsets
Solution Approach 1:
The rising threshold is set in advance at a safe distance above the falling threshold (e.g., 2.5V vs 1.5V, with a 1V margin). This preliminary positioning ensures that once a chip detects the rising threshold and enables falling threshold detection, there is sufficient voltage swing guaranteed to exceed any random comparator offset, ensuring reliable detection of the falling threshold that marks the timing period end.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures that all IC chips recognize the end of a timing period, maintaining synchronization and preventing system lock-ups or ping-pong effects, thereby ensuring correct and synchronized operation across multiple IC chips.
Implementation Method 1
external capacitor C1 to time an event... charging external capacitor C1 at a constant rate... detecting when external capacitor C1 has reached a threshold voltage
Data Source
AI summary
An IC chip, a system and a method of operating the IC chip in response to an event trigger are provided. The method includes responsive to the event trigger, coupling a pin to a source of constant current to charge an external capacitor coupled to the pin and monitoring a capacitor voltage on the pin. If the magnitude of the capacitor voltage is greater than a rising threshold, detection of a falling threshold is enabled. If the magnitude of the capacitor voltage is greater than a voltage threshold, a first response is triggered and the pin is coupled to the lower rail to discharge the external capacitor. If detection of the falling threshold is enabled and the magnitude of the capacitor voltage is less than the falling threshold, the first response is also triggered.