Single-Pin Strapping for Multi-Bit Chip Configuration
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Solution Overview
Problem
The existing methods for programming configuration vectors in integrated circuits require a large number of configuration pins, which increases the size and cost of chip packages and silicon dies, and are inefficient in reducing the number of pins needed for multi-bit configurations.
Innovation Solution
A method using a single digital I/O pin with external resistor dividers to present multiple voltage levels, allowing for the programming of multi-bit configuration vectors through pin-strapping, utilizing a configuration circuit that samples voltage at clocked intervals to determine the configuration vector.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple configuration pins are used for programming multi-bit configuration vectors, then the configuration capability and versatility are improved, but the chip package size and silicon die size increase
Solution Approach 1:
The patent combines multiple configuration bits into a single configuration pin by using external resistor dividers to present multiple voltage levels. Instead of requiring separate pins for each configuration bit, the invention merges the functionality of multiple pins into one by encoding configuration information in the voltage level presented to the configuration pin during sampling intervals.
Solution Approach 2:
The invention changes the parameter being measured from simple voltage presence/absence to multiple discrete voltage levels. By using external resistor dividers to create different voltage levels (e.g., 0V, VDD/2, VDD) that correspond to different configuration values, the system can encode multiple bits of configuration information in a single pin's voltage level.
2Adaptability or versatility
If multiple configuration pins are used for programming multi-bit configuration vectors, then the configuration capability is improved, but the number of pins and device complexity increase
Solution Approach 1:
The patent combines multiple configuration bits into a single configuration pin by using external resistor dividers to present multiple voltage levels. Instead of requiring separate pins for each configuration bit, the invention merges the functionality of multiple pins into one by encoding configuration information in the voltage level presented to the configuration pin during sampling intervals.
Solution Approach 2:
The configuration pin serves multiple functions: it can represent multiple configuration bits through different voltage levels, and it can be sampled at different time intervals to detect different configuration values. This multi-functionality reduces the total number of pins required while maintaining full configuration capability.
3Device complexity
If a single configuration pin with voltage level detection is used, then the number of pins is reduced, but the measurement precision requirements increase
Solution Approach 1:
The patent introduces external resistor dividers as intermediary components that convert digital configuration values into distinct analog voltage levels. These resistor dividers act as mediators between the configuration logic and the configuration pin, providing well-defined voltage levels that are easier to detect with standard digital logic than trying to directly measure multiple bits.
Solution Approach 2:
The invention replaces the mechanical/digital approach of using multiple pins with discrete voltage states with an analog approach using continuous voltage levels. By substituting the mechanical pin-by-pin configuration method with analog voltage level detection, the system achieves pin reduction while the sampling circuitry maintains sufficient precision through clocked sampling at defined intervals.
4Area of stationary object
If pin-strapping with external resistor dividers is used, then the chip size and cost are reduced, but the ease of manufacture may be affected
Solution Approach 1:
The patent performs configuration voltage level preparation in advance by using external resistor dividers that are pre-configured on the application board rather than requiring complex on-chip configuration circuitry. The resistor divider networks are established before the chip operates, allowing the chip to simply sample the pre-prepared voltage levels without needing complex internal configuration generation logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of configuration pins required, enabling efficient programming of multiple configuration vectors using standard digital logic, thereby minimizing chip size and cost while maintaining flexibility in chip operations.
Implementation Method 1
monitoring a voltage of the configuration circuit at clocked time intervals, and determining a configuration vector by identifying the clocked time interval at which a threshold voltage has been reached
Data Source
AI summary
A chip configured with pin-strapping includes a configuration pin coupled to a resistor, the resistor coupled a configuration circuit configured to provide a threshold voltage at a sense time interval. A configuration vector may be determined by driving the configuration pin with high impedance, and sampling the configuration pin at sense time intervals such that the configuration vector corresponds to the time interval at which a threshold voltage is reached.