Single-Pin Clock Gating for Multi-Domain IC Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated circuit testing methods require multiple external pins for clock domains, limiting parallelism and increasing processing time, and existing tools for managing internal clocks during testing result in area overhead and synthesis issues.
Innovation Solution
A system using a single external pin with a multiplexer and a dedicated flip-flop for clock gating, allowing control of various clocks from a single pin, enabling 'at speed' testing without timing problems and reducing area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple external pins are used for clock domains, then each clock domain can be tested independently, but the number of external pins increases and parallelism is limited
Solution Approach 1:
The patent combines multiple clock domain control functions into a single external pin. A multiplexer selects which internal clock signal to route to the scan path based on the test mode signal, while a dedicated flip-flop generates gating signals for multiple clock domains simultaneously. This merging approach reduces the number of external pins from multiple dedicated clock pins to a single shared pin that controls all clock domains during testing.
Solution Approach 2:
The single external pin serves multiple functions: it provides clock gating control for multiple different clock domains, selects which clock signal is active during testing, and enables parallel testing across all clock domains. The dedicated flip-flop and multiplexer work together to make this single pin universal for controlling all clock domains during scan testing operations.
2Reliability
If multiple external pins are used for clock domains, then each clock domain can be controlled separately, but processing time increases
Solution Approach 1:
The patent merges the control of multiple clock domains into a single synchronized mechanism. The dedicated flip-flop receives a single clock signal and generates gating signals for all clock domains simultaneously, allowing parallel testing across all domains without the sequential overhead of switching between multiple external pins. This combining approach reduces processing time by enabling concurrent operation.
3Adaptability or versatility
If existing tools for managing internal clocks are used, then clock domains can be controlled during testing, but area overhead increases
Solution Approach 1:
The patent extracts the essential clock gating function into a dedicated flip-flop that is specifically designed for this purpose. Rather than using complex existing tools or general-purpose clock management circuits, the invention isolates the core function of generating gating signals for multiple clock domains into a single dedicated flip-flop element, minimizing area overhead while maintaining full adaptability for testing all clock domains.
Data Source
AI summary
A system for testing an integrated circuit including components for receiving clock signals corresponding to different clock domains includes a pin of the integrated circuit to receive a test clock signal for components included in different clock domains, clock gating cells integrated in the integrated circuit to direct said test clock signal from the pin towards components included in respective clock domains and, coupled to each of the gating cells, a dedicated flip-flop for a respective clock domain, the dedicated flip-flop being also integrated in the integrated circuit to effect on the cell to which it is coupled a clock gating function during testing of the integrated circuit.