Single-Pin Clock Input for IC Test and System Timing
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Solution Overview
Problem
The increasing complexity and miniaturization of integrated circuits have made it challenging to provide necessary electrical connections, requiring additional terminals for testing and program debug, particularly for timing signals, which is inefficient and resource-intensive.
Innovation Solution
Forcing the system clock and test clock to the same frequency by overdriving the phase locked loop or crystal oscillator circuit, allowing a single terminal to supply both clock signals and eliminating the need for separate terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate terminals are used for system clock and test clock signals, then the integrated circuit can receive both clock signals independently, but the number of terminals required increases
Solution Approach 1:
The patent combines the system clock signal and test clock signal into a single terminal (TDO) by using a multiplexer to selectively route either signal through the same physical connection, thereby reducing the number of terminals while maintaining the ability to receive both clock signals independently when needed
Solution Approach 2:
The single terminal (TDO) is designed to serve multiple functions by accepting both system clock signals and test clock signals through time-multiplexed routing, making the terminal universal and eliminating the need for separate dedicated terminals for each clock signal
2Adaptability or versatility
If additional terminals are provided for testing and program debug, then the testing capability is enhanced, but the integrated circuit size increases
Solution Approach 1:
The patent merges multiple testing and debugging functions into existing terminals by implementing time-multiplexed signal routing, allowing test clock signals, system clock signals, and data signals to share the same physical terminal (TDO), thereby enhancing testing capability without increasing integrated circuit size
Solution Approach 2:
Existing terminals are designed to perform multiple functions including system operation, testing, and program debugging through configurable signal routing, eliminating the need for additional dedicated testing terminals and reducing the overall integrated circuit area required
3Reliability
If separate components are used for system clock and test clock generation, then each clock can be optimized independently, but the number of components increases
Solution Approach 1:
The patent merges the functionality of separate clock generation components into a unified system where a single terminal (TDO) and multiplexer structure handles both system clock and test clock signals, reducing the number of components while maintaining independent optimization capability through software-configurable routing
Data Source
AI summary
In a configuration testing integrated circuits, the system clock signals are forced to the same frequency as the test clock signals. When the test clock signals and the system clock signals have the same frequency, both clock signals can applied to the integrated circuit through a single terminal, whereby providing a terminal for the exchange of other signals with the integrated circuit. Using the same signals for test and system clocks allows selected components to be eliminated.