Single-Pin Interface Circuit for Electronic Device Testing

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Solution Overview

Problem

Electronic devices with limited pins, particularly in automotive and sensor applications, face challenges in testing due to the requirement of four pins for scan shift interface, which is not feasible, and existing solutions for single-pin communication do not effectively apply test patterns or capture responses.

Innovation Solution

A method using a data stream with three level bands is input through a single logic pin, decoding signals like scan_in, scan_shift_enable, and scan_clock, and generating a scan_out signal, enabling the transmission of these signals over a single wire through a duplex interface circuit with a level detection circuit and decoder.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If four pins are used for scan shift interface, then testing capability is improved, but device complexity increases

Engineering Contradiction:
Improvetesting capabilityVSAvoidnumber of pins
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent combines multiple control signals (scan clock, scan in, scan shift enable, scan out) into a single data stream transmitted over one pin. The interface circuit multiplexes these functions by encoding them as different voltage levels (three-level signal) within the data stream, allowing one pin to perform the work of four pins.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from spatial multiplexing (separate pins for separate signals) to temporal/encoding multiplexing (multiple signals encoded in time and voltage levels within a single stream). By using three voltage levels instead of binary states, the system encodes multiple control signals within a single data stream, effectively adding a dimension of signal encoding.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If single pin interface is used, then device complexity is reduced, but testing capability deteriorates

Engineering Contradiction:
Improvenumber of pinsVSAvoidtesting capability
Core Design Contradiction:
Device complexityVSEase of operation

Solution Approach 1:

The patent segments the data stream into distinct temporal slots, each carrying a specific control signal (scan clock, scan in, scan shift enable, or scan out). The interface circuit identifies which signal is being transmitted at each time step, allowing the single pin to independently control all scan shift register operations that would traditionally require multiple pins.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter of signal encoding from binary (two voltage levels) to ternary (three voltage levels). This allows the single data stream to encode multiple control signals simultaneously by varying the voltage level, thereby maintaining full testing capability while using only one pin.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If fixed baud rate interface is used, then communication is simplified, but adaptability deteriorates

Engineering Contradiction:
Improveinterface circuit complexityVSAvoidtest pattern length adaptability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent implements a dynamic interface where the data stream can adapt its structure based on the test pattern length. The interface circuit detects the scan_shift_enable signal to identify the start of test pattern transmission and automatically adjusts the timing and decoding accordingly. This allows the same single-pin interface to handle variable-length test patterns without requiring fixed baud rate configurations or complex reconfiguration.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10627445B2Method for testing an electronic device and an interface circuit therefore
Publication Date: 2020.04.21 TDK MICRONAS GMBH
  • US10627445B2 patent drawing
  • US10627445B2 patent drawing
  • US10627445B2 patent drawing

AI summary

A method and interface circuit for testing an electronic device with a single logic pin is disclosed. The comprises forming a data stream having three level bands; inputting the data stream through a single logic pin; and decoding the data stream to identify a scan_in signal, a scan_shift_enable signal and a scan_out signal and returning contemporaneously a scan_out signal as an output through the same logic pin. The interface circuit includes a decoder connected to the single logic pin.