Single-Pin Low Power Mode Control With Level-Shift Pull-Down
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Solution Overview
Problem
Existing integrated circuit (IC) power management systems lack efficiency in managing multiple low-power modes, requiring multiple pins and complex logic to control different power conservation states, which increases pin usage and reduces versatility.
Innovation Solution
An integrated circuit (IC) with a single pin for low power mode (LPM) control logic that uses a level shift with pull-down to manage both retention and sleep modes, allowing a single IC design to be used in various systems with different power budgets by selectively connecting to either retention or sleep mode enable pins on a power management IC (PMIC).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple pins and complex logic are used to control different power conservation states, then power management capability is improved, but pin usage increases and versatility decreases
Solution Approach 1:
The patent implements a universal low power mode control pin that can selectively control multiple different low power modes (retention mode, sleep mode, shutdown mode) depending on the PMIC configuration. This single multi-functional pin replaces what would traditionally require multiple dedicated pins for each power mode, thereby improving versatility while reducing pin usage.
Solution Approach 2:
The patent merges the control functions for multiple low power modes into a single control pin and associated logic circuitry. The LPM control logic consolidates the control signals for retention mode, sleep mode, and shutdown mode into one unified control mechanism, reducing the overall pin count and simplifying the device interface.
2Adaptability or versatility
If multiple pins and complex logic are used to control different power conservation states, then power management capability is improved, but device area increases
Solution Approach 1:
The LPM control logic implements a universal control mechanism that can manage multiple low power modes through a single control pin, eliminating the need for separate control circuits for each power mode. This multi-functional approach reduces the overall device area while maintaining comprehensive power management capability.
Solution Approach 2:
The patent combines the control logic for retention mode, sleep mode, and shutdown mode into a single integrated LPM control logic block. This consolidation merges multiple previously separate control circuits into one unified structure, thereby reducing device area while preserving full power management functionality.
3Adaptability or versatility
If a single pin is used for LPM control, then pin usage is reduced and versatility is improved, but control reliability may worsen due to voltage threshold issues
Solution Approach 1:
The patent introduces an intermediary isolation circuit with a level shifter and pull-down transistor between the LPM control pin and the LPM control logic. This intermediary structure mediates the voltage signal, ensuring reliable interpretation of the control signal across different voltage domains and preventing false triggering, thereby maintaining control reliability while using a single pin.
Solution Approach 2:
The pull-down transistor in the isolation circuit provides preliminary anti-action by actively pulling the voltage down to a defined low state before the main control logic samples the signal. This pre-conditioning of the signal prevents ambiguous voltage states and ensures reliable control signal interpretation, addressing potential reliability issues before they can affect system operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces pin usage and improves versatility by enabling a single IC to control different low power modes with reduced pin count and area usage, avoiding the need for glue logic and ensuring reliable operation across various power states.
Implementation Method 1
The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation
Implementation Method 2
The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM control logic output falling below a threshold
Data Source
AI summary
In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.