Single-Pin Power Reset and Status Circuit with Time-Multiplexed Signaling

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Solution Overview

Problem

Conventional power management circuits require multiple pins and suffer from signal routing issues due to the need for separate interface pins for power on reset and fault monitoring, leading to larger packaging and complexity.

Innovation Solution

A system and method that utilize a single output electrode of an integrated circuit to provide a status signal with time multiplexed states, indicating power on reset and operation statuses, through shorter and longer delay circuitry and encoding circuitry, to convey enable and ready signal states efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate interface pins are used for each voltage source enablement and fault monitoring, then power management control and status monitoring are achieved, but package size increases and signal routing becomes complex

Engineering Contradiction:
Improvepower management controlVSAvoidpackage size
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple power management functions (power on reset control and status monitoring) into a single shared interface pin. The circuit uses time-multiplexing to sequentially provide different functions through the same pin: first providing power on reset control, then providing status signals indicating voltage regulator readiness and fault conditions. This merging eliminates the need for separate pins for each function, reducing package size and simplifying signal routing while maintaining full control and monitoring capabilities.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared interface pin is designed to perform multiple functions depending on the operational state of the voltage regulators. The pin can provide power on reset control when regulators are initializing, and subsequently provide status monitoring when regulators are operational. The circuit internally manages this multi-functionality through state detection and signal routing logic, allowing one pin to replace what would traditionally require multiple dedicated pins.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If separate interface pins are used for each voltage source enablement and fault monitoring, then power management control and status monitoring are achieved, but signal routing becomes complex

Engineering Contradiction:
Improvestatus monitoringVSAvoidsignal routing
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple signal routing paths into a single shared interface pin. Internally, the circuit uses time-multiplexing to route different signals through the same pin at different times: power on reset signals during initialization, and status signals during operation. This approach simplifies external signal routing while maintaining the ability to monitor multiple voltage sources and provide control functions through the unified interface.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The circuit employs periodic time-multiplexed action to sequentially provide different functions through the shared pin. The system alternates between providing power on reset control and providing status monitoring signals based on the operational state of the voltage regulators. This periodic switching of functions through the same physical interface simplifies routing complexity while maintaining comprehensive control and monitoring capabilities.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS7788515B2Power control and status circuitry for communicating power on reset control and status via a single electrode
Publication Date: 2010.08.31 NAT SEMICON CORP
  • US7788515B2 patent drawing
  • US7788515B2 patent drawing
  • US7788515B2 patent drawing

AI summary

A system and method providing, via a single output electrode of an integrated circuit having internal circuitry, a status signal having time multiplexed states indicative of a power on reset condition for external circuitry following enablement of operations of portions of the internal circuitry, and further indicative of subsequent operation statuses of the internal circuitry portions.