Single PLL Clock Generation for Multimedia Pixel and Transmission Signals
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Solution Overview
Problem
Conventional multimedia systems require multiple phase-locked loops (PLLs) for clock signal generation, leading to increased size, power consumption, and potential signal interference, while also being inefficient in adapting to varying color depths for data transmission.
Innovation Solution
Generating a transmission clock signal from a reference clock signal and then producing a pixel clock signal through division or multiplication, using a single PLL to reduce the number of PLLs required and allowing for adaptive frequency adjustment based on color depth, thereby optimizing clock signal generation for multimedia data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple phase-locked loops (PLLs) are used for clock signal generation, then clock signal generation capability is improved, but device size increases
Solution Approach 1:
The patent combines multiple PLL functions into a single PLL by using frequency multiplication and division circuits. Instead of employing separate PLLs for different clock signals (pixel clock and transmission clock), the invention uses one PLL to generate a base clock signal that is then processed through frequency multiplication and division to derive both required clock signals, thereby reducing device size while maintaining clock generation capability
Solution Approach 2:
The single PLL in the patent serves multiple functions by generating a master clock signal that is subsequently used to derive both the pixel clock and transmission clock through frequency processing circuits. This multi-functional approach allows one PLL to replace what would traditionally require multiple dedicated PLLs, reducing overall device footprint
2Reliability
If multiple phase-locked loops (PLLs) are used for clock signal generation, then clock signal generation capability is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple PLL power consumption into a single PLL by consolidating clock generation functions. The frequency multiplication and division circuits consume less power than additional PLLs, making this approach more energy-efficient while maintaining the ability to generate multiple clock signals with different frequencies
Solution Approach 2:
The single PLL performs multiple clock generation tasks through frequency processing, reducing the total power consumption compared to having separate PLLs for each clock signal. The universal PLL generates a master clock that is then adapted to different frequencies through lower-power multiplication and division circuits
3Reliability
If multiple phase-locked loops (PLLs) are used for clock signal generation, then clock signal stability is improved, but signal interference increases
Solution Approach 1:
The patent reduces signal interference by using a single PLL as a common source for both pixel clock and transmission clock signals. This eliminates the potential for interference between multiple independent PLLs while maintaining stability through frequency multiplication and division, which preserve the phase coherence from the single master clock source
4Device complexity
If conventional clock generation methods are used, then clock signal generation is simple, but adaptability to varying color depths is reduced
Solution Approach 1:
The patent implements dynamic adaptability by using frequency multiplication and division circuits that can be configured based on color depth requirements. The system can dynamically adjust the output frequencies of the pixel clock and transmission clock by changing the multiplication and division factors, allowing adaptation to different color depths without requiring multiple fixed-frequency PLLs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of PLLs needed, minimizing size and power consumption while enabling efficient data transmission by dynamically adjusting pixel clock frequencies according to color depth, thus enhancing the multimedia system's performance and reliability.
Implementation Method 1
a transmission clock signal that has a first frequency is generated by multiplying a reference clock signal that has a second frequency that is different than the first frequency
Implementation Method 2
the generated transmission clock signal is multiplied to generate a pixel clock signal that has a third frequency that is different than the first and second frequencies
Data Source
AI summary
Methods of generating a pixel clock signal for a multimedia source are provided in which a transmission clock signal having a first frequency is generated from a reference clock signal that has a second frequency. The generated transmission clock signal is multiplied by a multiple to generate the pixel clock signal. The pixel clock signal has a third frequency that is the product of the second frequency and the multiple.