Single-PLL Clock Calibration for Two-Chip Die Skew
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Solution Overview
Problem
In two-chip die modules, clock skew occurs due to variations in chip processing, power supply setpoints, and package signal propagation asymmetries, leading to compromised latch setup and hold timing margins, necessitating a method to calibrate the arrival times of launch and capture clocks to minimize chip-to-chip timing effects.
Innovation Solution
A method involving a single phase lock loop (PLL) providing a common clock signal to both chips, with programmable delay units and skew adjust and phase detect units to equalize clock signal travel distances and minimize delay differences, along with a built-in self-test engine for error checking and data pattern generation to quantify and null out clock skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single PLL provides common clock signals to both chips, then clock synchronization is improved, but chip-to-chip clock skew increases due to signal propagation asymmetries
Solution Approach 1:
The patent adjusts the clock signal propagation parameters by introducing programmable delay units that can modify the timing characteristics of clock signals. These delay units allow dynamic adjustment of clock arrival times at each chip, compensating for propagation asymmetries and achieving precise synchronization while maintaining a single PLL architecture.
Solution Approach 2:
The patent introduces an intermediary calibration mechanism that measures and compensates for clock skew between chips. This intermediary system includes delay measurement circuits and control logic that act as mediators between the single PLL source and the two chips, adjusting timing to eliminate skew effects.
2Manufacturing precision
If clock signal travel distances are equalized, then clock skew is reduced, but device complexity increases due to programmable delay units and skew adjust circuits
Solution Approach 1:
The patent implements self-service through built-in delay measurement circuits that automatically detect clock skew conditions and trigger appropriate compensation actions. The system performs self-calibration by measuring actual propagation delays and adjusting programmable delay units without requiring external intervention, thereby reducing the operational complexity despite the added hardware.
Solution Approach 2:
The patent employs feedback mechanisms where clock skew is continuously monitored and the programmable delay units are dynamically adjusted based on measured conditions. This closed-loop control system uses feedback from delay measurement circuits to automatically compensate for timing variations, making the complexity management more systematic and less manual.
3Reliability
If latch setup and hold timing margins are maintained, then reliability is improved, but clock distribution flexibility is reduced due to strict timing requirements
Solution Approach 1:
The patent introduces dynamic adjustment capabilities through programmable delay units that can adaptively modify clock timing based on actual propagation conditions. This dynamic system allows the clock distribution network to maintain reliable latch timing margins while simultaneously adapting to different chip configurations and signal path variations, thereby preserving flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes chip-to-chip clock skew, ensuring synchronized clock signals and maintaining timing margins by calibrating clock arrival times, thus enhancing the performance of high-speed interfaces in two-chip die modules.
Implementation Method 1
a phase detector in a feedback loop. The oscillator generates a periodic signal and the phase detector compares the phase of that signal with the phase of the input periodic signal
Implementation Method 2
adjusting the oscillator to keep the phases matched
Implementation Method 3
skew adjust and phase detect units to equalize clock signal travel distances and minimize delay differences
Data Source
AI summary
A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.