Single-PLL RF Power Control for Synchronized Multi-Channel Outputs
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Solution Overview
Problem
Existing radio frequency (RF) signal generators face challenges in scalability, operational robustness, frequency precision, application flexibility, manufacturing complexity, and cost due to the need for multiple phase-locked loops (PLLs) to synchronize multiple RF output signals, which leads to high design and manufacturing complexity, susceptibility to noise and thermal drift, and increased costs.
Innovation Solution
A control unit and RF power generator that uses a single phase-locked loop (PLL) control mechanism to synchronize multiple RF output signals by comparing a reference signal with a feedback signal, generating error signals, and adjusting waveform tuning signals to minimize differences, allowing for synchronized RF output signals with precise frequency, phase, and amplitude, while using a single control loop to manage multiple channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple phase-locked loops are used to generate multiple RF output signals, then each RF output signal can be synchronized, but the device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent combines multiple phase-locked loops into a single phase-locked loop structure. The single PLL generates a common phase reference signal that is distributed to multiple RF output channels, eliminating the need for separate PLLs in each channel while maintaining synchronization across all outputs.
Solution Approach 2:
The single phase-locked loop is designed to serve multiple functions simultaneously by providing a common phase reference to multiple RF output channels. This universal reference signal enables synchronization across all channels without requiring dedicated PLLs for each function.
2Reliability
If multiple phase-locked loops are used for each RF output signal, then synchronization is achieved, but the manufacturing cost increases
Solution Approach 1:
Multiple expensive PLL circuits are merged into a single PLL circuit that serves all RF output channels. This consolidation reduces the total component count, simplifies manufacturing, and lowers cost while preserving synchronization accuracy through the common phase reference.
3Measurement precision
If multiple phase-locked loops are used to synchronize RF signals, then frequency precision is maintained, but the system becomes susceptible to noise and thermal drift
Solution Approach 1:
Multiple independent PLLs are replaced with a single PLL, reducing the number of oscillators and feedback circuits that can introduce noise and thermal drift. The unified structure minimizes cumulative errors while maintaining frequency precision through a single stable reference.
4Device complexity
If a single phase-locked loop is used to control multiple RF output signals, then device complexity is reduced, but maintaining synchronization across all channels becomes challenging
Solution Approach 1:
The patent segments the RF output system into multiple independent channels that all receive input from a single common phase reference. Each channel can be independently configured for different frequencies and amplitudes while maintaining phase coherence through the shared reference signal.
Solution Approach 2:
The single phase-locked loop is designed as a universal reference generator that can simultaneously support multiple RF output channels with different frequency and amplitude requirements, ensuring synchronization across all channels through the common phase reference.
Data Source
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AI summary
The invention describes a control unit (2, 21) for generating a plurality of synchronized radio frequency (RF) output signals (RFout,i) each having a respective output frequency (fi), phase (Φi), and amplitude (Ai), comprising: a signal comparator (3) configured to compare a reference signal (4) having a reference frequency (fref) and a reference phase (Φref) with a feedback signal (5) having a feedback frequency (fPLL) and a feedback phase (ΦPLL), and configured to generate an error signal (6, 6') representative of a difference between the reference signal (4) and the feedback signal (5); and a data processing unit (7) receiving as an input signal the error signal (6, 6') generated by the signal comparator (3), and outputting a plurality of waveform tuning signals (FTWPLL, FTWi) as a function of the error signal (6, 6'); wherein a plurality of waveform generators (DDSPLL, DDSi) each receiving at least one of the plurality of waveform tuning signals (FTWPLL, FTWi) output by the data processing unit (7), wherein each waveform generator (DDSPLL, DDSi) generates a time-dependent amplitude signal (APLL(t), Ai(t)) as a function of the received respective waveform tuning signal (FTWPLL, FTWi), wherein one predetermined amplitude signal (APLL(t)) of the generated plurality of amplitude signals (APLL(t), Ai(t)) represents the feedback signal (5) input to the signal comparator (3), and the other amplitude signals (Ai(t)) represent the respective radio frequency (RF) output signals (RFout,i) to be generated, and wherein the data processing unit (7) is configured to adjust both the waveform tuning signal (FTWPLL) corresponding to the one predetermined amplitude signal (APLL(t)) representing the feedback signal (5) such as to minimize the error signal (6, 6'), and the other waveform tuning signals (FTWi) corresponding to the other amplitude signals (Ai(t)) representing the radio frequency (RF) output signals (RFout,i) based on the adjusted waveform tuning signal (FTWPLL) of the predetermined amplitude signal (APLL(t)) representing the feedback signal (5). The invention further describes a radio frequency (RF) power generator (1, 20, 30), an arrangement (35, 40, 45, 50, 55) of at least two such radio frequency (RF) power generators (1, 20, 30), and a method each for generating a plurality of synchronized radio frequency (RF) output signals (RFout,i).