Single-PLL Frequency Synthesizer for Low-Power UWB Hopping
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Solution Overview
Problem
Existing frequency synthesizers for ultra-wide-band (UWB) communications systems face challenges in achieving low power consumption, low complexity, and small area occupation while meeting the stringent frequency hopping requirements, often resulting in high power consumption and complex designs due to the need for multiple PLL circuits and high Q-index filters.
Innovation Solution
A frequency synthesizer architecture incorporating a single VCO, a PLL system, two SSB mixers, and a multiplexer, with even-number frequency division to generate I/Q signals, allowing for low Q-factor filtering and eliminating the need for poly-phase filters, thereby reducing complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple independent PLL circuits are used to achieve fast frequency hopping, then frequency hopping speed is improved, but power consumption and chip area increase significantly
Solution Approach 1:
The patent pre-generates I/Q signals at a lower frequency (528 MHz) using a single PLL, then uses mixers to up-convert these pre-generated signals to the required carrier frequencies. This preliminary generation of base signals eliminates the need for multiple PLLs to simultaneously generate all carrier frequencies, thereby reducing power consumption while maintaining fast frequency hopping capability through the mixer-based frequency conversion.
2Speed
If multiple independent PLL circuits are used to achieve fast frequency hopping, then frequency hopping speed is improved, but chip area occupation increases
Solution Approach 1:
The patent merges the frequency generation function into a single PLL that produces base I/Q signals, then combines these signals with frequency division outputs through mixers to generate all required carrier frequencies. This consolidation of the PLL into a single unit while using mixers for frequency multiplication significantly reduces chip area compared to using multiple independent PLL circuits, each occupying separate space.
3Device complexity
If a single PLL is used with non-integer frequency division, then device complexity is reduced, but manufacturing precision and signal quality deteriorate due to inability to generate exact 90-degree phase difference
Solution Approach 1:
The patent segments the frequency generation process into two independent parts: (1) a single PLL generating base I/Q signals at 528 MHz with exact 90-degree phase difference, and (2) mixer-based up-conversion to generate the final carrier frequencies. This segmentation allows the PLL to operate at a lower frequency where precise phase generation is easier, while the mixer handles the frequency multiplication, thereby maintaining both low device complexity and high phase precision.
4Measurement precision
If high Q-index filters are used to suppress image signals, then signal quality is improved, but device complexity and area occupation increase
Solution Approach 1:
The patent changes the operating parameters of the mixer by carefully selecting the frequencies of the input signals (baseband I/Q signals and frequency division outputs) to position the image signals far from the desired output frequencies. This parameter optimization reduces the Q-index requirement of the filters, allowing the use of simpler, lower-order filters that consume less power and occupy less area while still achieving adequate image signal suppression.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves high integration, low complexity, and low power consumption, enabling efficient frequency hopping with reduced design complexity and area occupation, while employing simple narrowband filters and avoiding the need for poly-phase filters.
Implementation Method 1
a voltage controlled oscillator (VCO) is used for generating an oscillating frequency foc according to a voltage control signal
Implementation Method 2
The PLL system includes a first frequency divider which divides the oscillating frequency by 10 and generates a first dividing signal. PLL also locks the voltage control signal according to the first dividing signal frequency and reference signal frequency
Implementation Method 3
The first SSB mixer connects to the second frequency divider and used for mixing the second dividing signal and the third dividing signal to generate a first mixing signal
Data Source
AI summary
A frequency synthesizer applied to a frequency hopping system includes a voltage controlled oscillator (VCO), a phase lock loop (PLL) system, a second frequency divider, a first SSB mixer, a second SSB mixer, and a multiplexer. The VCO generates an oscillating frequency. The PLL system includes a first frequency divider and divides the oscillating frequency by 10 to generate a first dividing signal. The second frequency divider divides the oscillating frequency by 2 to generate a second dividing signal and further divides the second dividing signal by 2 to generate a third dividing signal. The first SSB mixer mixes frequencies of the second and third dividing signals to generate a first mixing signal. The second SSB mixer mixes frequencies of the first mixing signal and the first dividing signal to generate a second mixing signal. The Multiplexer determines to output the first mixing signal or the second mixing signal.