Single Poly EEPROM Cell With Integrated Read Transistor
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Solution Overview
Problem
Existing single poly EEPROM cells with segregated read transistors face challenges in reducing area and experiencing asymmetric stress during programming and erasing operations, which affects reliability and fabrication complexity.
Innovation Solution
Integration of a read transistor within a control gate or erase gate well in a single poly EEPROM cell, allowing for reduced area and symmetric stress on the read transistor gate dielectric, enabling the use of a common dielectric layer and potentially lowering fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a segregated read transistor is used in a single poly EEPROM cell, then the read operation can be performed independently, but the total area of the EEPROM cell increases
Solution Approach 1:
The patent merges the read transistor with the control gate well structure by integrating the read transistor's source and drain regions directly into the control gate well. This consolidation eliminates the need for a separate read transistor structure, thereby reducing the total cell area while preserving the independent read operation capability through shared well infrastructure.
Solution Approach 2:
The control gate well serves multiple functions: it acts as both the control gate structure and the source/drain region for the read transistor. This multi-functional design allows the same physical structure to perform both control gate operations and read transistor operations, eliminating redundant components and reducing overall cell area.
2Ease of operation
If a segregated read transistor is used in a single poly EEPROM cell, then the read function is distinct, but the fabrication complexity increases
Solution Approach 1:
By combining the read transistor source/drain regions with the control gate well formation steps, the patent reduces the number of separate fabrication processes. The same ion implantation and diffusion steps that create the control gate well also establish the read transistor regions, simplifying the overall fabrication sequence while maintaining distinct read functionality.
Solution Approach 2:
The control gate well structure performs dual roles as both the control gate and the read transistor active region. This universality allows a single fabrication process to create both structures simultaneously, reducing fabrication complexity while preserving the distinct read function through appropriate doping and geometric design.
3Productivity
If asymmetric stress is applied during programming and erasing operations, then the EEPROM can be programmed and erased, but the reliability of the read transistor gate dielectric decreases
Solution Approach 1:
The patent employs asymmetric doping profiles within the control gate well, creating intentionally asymmetric stress distributions during programming and erasing operations. This controlled asymmetry allows the EEPROM to perform programming and erasing functions while the symmetric well structure ensures that the read transistor gate dielectric experiences balanced stress, thereby maintaining reliability.
Solution Approach 2:
Different regions of the control gate well are doped with different concentrations and types of dopants to create locally optimized stress conditions. The regions adjacent to the read transistor gate dielectric are specifically engineered to provide symmetric stress balancing, while other regions accommodate the asymmetric stress needed for programming and erasing operations.
Data Source
AI summary
A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.