Single Poly EEPROM Using NMOS Program Transistor and Well Bias
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Solution Overview
Problem
Existing EEPROM devices face challenges in achieving high density and efficient programming/erase operations due to complex processes, high costs, and poor data retention, primarily because they require special materials and additional capacitors that increase size and degrade endurance.
Innovation Solution
The solution involves using an NMOS program transistor and a PMOS control capacitor with well bias to generate multiple sources of hot electrons for programming, reducing the need for additional capacitors and optimizing the coupling ratio for faster erase operations, thereby improving programming speed and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If prior art stacked/split gate EEPROM technology is used, then programming and erase operations can be performed, but process complexity and manufacturing cost increase due to special multi-polysilicon materials, different gate oxide thicknesses, and modified doping profiles
Solution Approach 1:
The patent uses a uniform single-polysilicon gate structure throughout the device, eliminating the need for multiple polysilicon layers with different properties. This homogeneous approach maintains programming/erase functionality while simplifying the manufacturing process to use standard single-polysilicon CMOS technology.
Solution Approach 2:
The single polysilicon gate serves multiple functions: it acts as both the control gate and the floating gate, eliminating the need for separate multi-polysilicon structures. This universal gate structure performs all necessary functions for EEPROM operation using a single material system.
2Reliability
If additional capacitors are added to improve programming and erase operations, then operational performance improves, but device area increases and density decreases
Solution Approach 1:
The patent merges the control gate and floating gate into a single polysilicon gate structure, eliminating the need for separate capacitor components. This integration achieves the necessary electrical coupling for programming and erase operations without requiring additional discrete capacitors, thereby reducing device area.
Solution Approach 2:
The single polysilicon gate performs multiple functions including control gate functionality and floating gate functionality, eliminating the need for separate capacitor structures that would be required in traditional designs to achieve the same operational performance.
3Productivity
If additional capacitors are used to optimize coupling ratio, then erase operation speed improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent optimizes the physical dimensions and electrical parameters of the single polysilicon gate structure itself to achieve the desired coupling ratio for fast erase operations, rather than adding complex capacitor networks. This includes adjusting gate length, width, and oxide thickness parameters within the single-gate structure.
4Reliability
If PMOS transistors are used for programming, then programming can be performed, but programming speed and efficiency are limited compared to NMOS-based approaches
Solution Approach 1:
The patent inverts the conventional approach by using an NMOS transistor instead of a PMOS transistor as the program transistor. This inversion leverages the superior hole injection characteristics of NMOS devices to achieve faster and more efficient programming speeds while maintaining reliable programming capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances programming speed, reduces power consumption, and increases memory cell endurance by utilizing well bias to generate channel and second channel hot electrons, leading to improved EEPROM performance without the need for additional capacitors, thus achieving higher density and better data retention.
Implementation Method 1
utilizing well bias to generate channel and second channel hot electrons
Implementation Method 2
utilizing well bias to generate channel and second channel hot electrons
Implementation Method 3
Charges (in amounts that represent either a zero (0) representation or a one (1) representation) may be written to the floating gate
Implementation Method 4
Electrons on the floating gate 130 will pass through the gate oxide between the floating gate 130 and the control gate of the PMOS control capacitor 120 by Fowler-Nordheim (FN) tunneling process
Data Source
AI summary
A system and method is disclosed for providing a CMOS compatible single poly electrically erasable programmable read only memory (EEPROM) with memory cells that comprise an NMOS program transistor. In a first embodiment the memory cells of the EEPROM comprise a PMOS control capacitor. In a second embodiment the memory cells of the EEPROM comprise an NMOS control capacitor. A well bias voltage is applied to the NMOS program transistor instead of a gate bias voltage. The well bias voltage enables the injection of (1) channel hot electrons, (2) second hot electrons initiated by the channel hot electrons, and (3) drain impact ionization hot electrons into a floating gate of the NMOS program transistor.