Single-Poly EEPROM Cell With Voltage Divider for Low-Power Programming
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Solution Overview
Problem
Existing single polycrystalline silicon EEPROM cells require separate control circuits and substantial layout area for complementary floating gates, and suffer from high power consumption and reduced reliability due to edge-dependent current flow and voltage stress on unselected cells.
Innovation Solution
The EEPROM array architecture incorporates a single polycrystalline silicon gate memory cell with a voltage divider and sense transistor, utilizing Fowler-Nordheim tunneling for programming and erase operations, which reduces power requirements and eliminates the need for high voltage supplies, and includes a switch and access transistor configuration to minimize stress on unselected cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complementary floating gates are used in prior art EEPROM cells, then programming capability is achieved, but layout area increases substantially
Solution Approach 1:
The patent extracts and eliminates one of the two complementary floating gates from the EEPROM cell structure. By removing the redundant floating gate, the design achieves programming capability without requiring both complementary floating gates, thereby substantially reducing the layout area while maintaining the essential memory function.
2Reliability
If large drain-extended transistors are used in prior art EEPROM cells, then punch through is prevented at high voltages, but device complexity increases
Solution Approach 1:
The patent replaces the complex large drain-extended transistor structures with simpler, standard CMOS transistors. By using conventional transistor designs instead of specialized high-voltage transistors, the invention maintains adequate performance while significantly reducing device complexity and manufacturing difficulty.
3Measurement precision
If separate control circuits are used for each cell in prior art EEPROM arrays, then cell control precision is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal control circuit that can manage multiple EEPROM cells through shared control lines and select signals. Instead of dedicating separate control circuits to each cell, the design uses a single control circuit with multi-functional capabilities, reducing overall complexity while maintaining precise cell control through selective addressing.
4Reliability
If high voltage supplies are used in prior art EEPROM cells, then programming is achieved, but power consumption increases
Solution Approach 1:
The patent changes the voltage parameter requirements for programming operations. By modifying the cell structure and control mechanisms, the invention enables programming to be achieved at lower voltages compared to traditional high-voltage supplies, thereby reducing power consumption while maintaining effective programming capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution decreases power consumption, increases program/erase cycles, and enhances reliability by achieving uniform current density and reducing voltage stress on unselected cells, thereby improving the overall performance and longevity of the memory cells.
Implementation Method 1
A single polycrystalline silicon EEPROM cell architecture that uses a voltage divider and access transistors to reduce power requirements through Fowler-Nordheim tunneling
Data Source
AI summary
An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIGS. 7 and 8) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (806) coupled to receive a first program voltage (PGMDATA) and a first select signal (ROWSEL). A voltage divider (804) is coupled in series with the switch. A sense transistor (152) has a sense control terminal (156) and a current path coupled between an output terminal (108) and a reference terminal (110). A first capacitor (154) has a first terminal coupled to the switch and a second terminal coupled to the sense control terminal. An access transistor (716) has a control terminal coupled to receive a read signal (721), and a current path coupled between the output terminal and a bit line (718).