Single-Poly EPROM With Additional Gate for Higher Coupling Ratio
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Solution Overview
Problem
Conventional single-poly EPROM devices require a large silicon area due to a low coupling ratio between the floating gate and the control gate, resulting in inefficient use of space compared to double poly EPROMs.
Innovation Solution
The introduction of an additional gate positioned above the floating gate, electrically connected to the control gate, increases the coupling ratio by adding capacitance without altering the manufacturing process, allowing for a smaller silicon area usage while maintaining or improving the coupling ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional single-poly EPROM structure is used with a large (n-) well diffusion under the floating poly, then the device can be manufactured with a single polysilicon layer, but the coupling ratio is low and the silicon area occupied is large (5 to 20 times larger than double poly EPROMs)
Solution Approach 1:
The patent introduces a third dimension by placing an additional gate structure above the floating gate, vertically stacking multiple functional layers. This vertical integration increases the coupling ratio without expanding the planar silicon footprint, effectively resolving the contradiction between manufacturing simplicity and area efficiency
2Reliability
If the control gate is formed by a large area (n-) well diffusion under the floating poly, then the coupling ratio can be maintained, but the silicon area required increases significantly
Solution Approach 1:
By adding the additional gate structure in the vertical dimension above the floating gate, the patent enhances the coupling ratio through increased capacitive coupling area without requiring lateral expansion of the (n-) well diffusion, thus maintaining reliability while reducing area
Solution Approach 2:
The additional gate structure is nested within the vertical stack above the floating gate, creating a compact configuration where multiple functional elements are integrated in a nested arrangement, maximizing coupling efficiency within a minimal footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the construction of single-poly EPROMs with a higher coupling ratio in a smaller area, potentially doubling the net capacitor values depending on the poly thickness and finger spacing, thus optimizing silicon usage and manufacturing efficiency.
Implementation Method 1
the additional gate and the floating gate are separated by an insulating layer... This leads to a higher coupling ratio between the floating gate and the control gate
Implementation Method 2
A thin gate oxide is provided as insulator between the floating gate 10 and the channel region
Implementation Method 3
The charges on the floating gate effect the conductance of the channel between the source and the drain of the field effect transistor
Data Source
AI summary
The invention relates to a single-poly EPROM comprising a source, a drain, a control gate, a floating gate and an additional gate. The control gate is positioned laterally of a channel between the source and the drain. The floating gate is positioned above the channel above the control gate. The additional gate is positioned above the floating gate, wherein the additional gate is electrically connected to the control gate.