Single-Poly Floating-Gate Memory Erase Voltage Reduction
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Solution Overview
Problem
Conventional single-poly nonvolatile memories are limited to one-time programming due to the inability to efficiently remove carriers from the floating gate, making them incompatible with standard CMOS manufacturing processes and lacking the erasable functionality required for multi-time programming applications.
Innovation Solution
The method involves fabricating an erasable programmable single-poly nonvolatile memory with two serially-connected PMOS transistors and an additional NMOS transistor with a floating gate, utilizing a thicker gate oxide layer for carrier injection and a thinner layer for carrier removal, integrated within a standard CMOS process, allowing for efficient erasure by adjusting the erase line voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional single-poly nonvolatile memory structure is used, then the manufacturing process is simpler and compatible with standard CMOS, but the memory can only be programmed once and cannot be erased
Solution Approach 1:
The gate oxide layer is segmented into two distinct regions: a first region with a first thickness for carrier injection and a second region with a second thickness for carrier removal. This segmentation allows the same floating gate structure to support both programming and erasing operations, enabling multi-time programming capability while maintaining CMOS compatibility
Solution Approach 2:
Different regions of the gate oxide layer are assigned different thicknesses to perform different functions. The first region (thicker) facilitates electron injection during programming, while the second region (thinner) enables electron removal during erasing. This local differentiation of structural properties allows the memory to be both programmable and erasable
2Reliability
If a dual-poly structure with separate control gate and floating gate is used, then programming functionality is achieved, but the fabrication process requires more steps and is incompatible with standard CMOS
Solution Approach 1:
The control gate and floating gate are merged into a single polysilicon gate structure. The gate oxide layer beneath this single gate is selectively thinned in certain regions to create the dual-function structure. This merging eliminates the need for separate gate formation steps while retaining the ability to program and erase through the differentiated oxide thickness
3Ease of manufacture
If a uniform thickness gate oxide layer is used, then the manufacturing process is simpler, but carrier removal for erasing is inefficient
Solution Approach 1:
The gate oxide layer is formed with non-uniform thickness: a first region with greater thickness for programming and a second region with lesser thickness for erasing. This local quality differentiation enables efficient carrier removal in the thinner region while maintaining programming capability in the thicker region, all within a single oxide formation process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables multi-time programming capabilities by reducing the erase line voltage, effectively changing the storage state of the nonvolatile memory while maintaining compatibility with standard CMOS manufacturing processes, thus overcoming the limitations of one-time programming.
Implementation Method 1
during the electrons are transmitted from the source line S to the drain line D through an n-channel region, the hot carriers (e.g. hot electrons) are attracted by the control voltage on the control gate 12 and injected into the floating gate 14
Implementation Method 2
the first region of the gate oxide layer has a first thickness and is used for carrier injection, and the second region of the gate oxide layer has a second thickness and is used for carrier removal
Data Source
Figure 1~2C
Figure 3A~3D
Figure 4
AI summary
The present invention provides method of fabricating an erasable programmable single-poly nonvolatile memory, comprising steps of: defining a first area (A) and a second area (B) in a first type substrate; forming a second type well region in the first area (A); forming a first gate oxide layer (342) and a second gate oxide layer (362) covered on a surface of the first area (A), wherein the second gate oxide layer (362) is extended to and is adjacent to the second area (B); forming a DDD region in the second area; etching a portion (362b) of the second gate oxide layer above the second area (B) which forms an erase gate region; forming two polysilicon gates (34, 36)covered on the first (342) and the second (32, 362a, 362b) gate oxide layers; and defining a second type doped region in the DDD region and a first type doped regions in the second type well region. The polysilicon gate (36) on the second gate oxide layer (362) forms a floating gate and the polysilicon gate (34) on the first gate oxide layer (342) forms part of a select transistor.