Single Poly Floating Gate Memory Cell Area Reduction
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Solution Overview
Problem
Existing Few Time Programmable (FTP) non-volatile memory devices occupy a large area due to the size of their memory cells, which limits their efficiency and requires improvements in cell area to enhance overall device performance.
Innovation Solution
The design of a single poly, floating gate FTP memory device with reduced dimensions, utilizing a floating gate MOS transistor and an access MOS transistor sharing a floating gate, allows for capacitive coupling to control gate voltage, enabling efficient reading, programming, and erasing operations through optimized biasing methods, including the Fowler-Nordheim effect for programming and erasing, and Band-to-Band Hot Electron effect for programming, without the need for selection transistors and related components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional FTP memory device structure with separate selection transistors is used, then the device can perform reading, programming, and erasing operations, but the memory cell area becomes large
Solution Approach 1:
The patent merges the selection transistor and storage transistor into a single integrated structure where the control gate serves dual purposes: selecting the memory cell and storing data. This consolidation eliminates separate selection transistors and reduces the number of required components, directly addressing the technical contradiction by reducing memory cell area while maintaining operational functionality through the shared control gate mechanism
Solution Approach 2:
The control gate is designed to perform multiple functions simultaneously: it acts as both the selection gate for activating specific memory cells and the storage element for retaining data through trapped charges. This multi-functionality allows the device to operate as both a selection mechanism and a storage unit, eliminating the need for separate selection transistors and thereby reducing overall cell area while preserving full read/write/erase capabilities
2Productivity
If the memory cell area is reduced, then the overall device efficiency improves, but the available space for other components decreases
Solution Approach 1:
By combining the selection and storage functions into a single integrated transistor structure, the patent reduces the memory cell footprint, which directly improves device efficiency and increases the proportion of active storage area. This merging allows more memory cells to be packed into the same chip area, enhancing overall productivity while the reduced cell size naturally increases available space for other components
3Area of stationary object
If selection transistors and related components are removed, then the memory cell area is reduced, but the device may lose operational functionality
Solution Approach 1:
The control gate is designed to perform multiple functions simultaneously: it acts as both the selection gate for activating specific memory cells and the storage element for retaining data through trapped charges. This multi-functionality ensures that removing separate selection transistors does not compromise operational functionality, as the control gate itself provides both selection and storage capabilities, maintaining reliable read/write/erase operations
Solution Approach 2:
The memory transistor structure is designed to be self-sufficient, where the control gate automatically performs both selection and storage functions without requiring external selection transistors. The device structure enables the control gate to self-manage both cell activation and data retention, ensuring operational reliability is maintained even with reduced component count
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a significant reduction in memory cell area, achieving up to 63% area savings, lower power consumption, and simplified high-voltage chains, while maintaining efficient operation and integration with CMOS/BCD technology.
Implementation Method 1
a floating gate region (21) formed in the same polysilicon layer as the control gate region (24, 25) and capacitively coupled to a control gate terminal (33)
Implementation Method 2
The storage transistor is both programmed and erased using the Fowler-Nordheim effect
Implementation Method 3
Band-to-Band Hot Electron effect for programming
Data Source
AI summary
In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.