Single-Poly Floating-Gate Transistor Erase Gate Substrate Design
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Solution Overview
Problem
Existing nonvolatile memory technologies, such as dual-poly and single-poly memories, face challenges in being erasable and compatible with standard CMOS manufacturing processes, limiting their multi-time programming capabilities.
Innovation Solution
The design of an erasable programmable single-poly nonvolatile memory that incorporates serially-connected PMOS transistors with polysilicon gates and an NMOS transistor, utilizing ion implantation and specific substrate structures to create an erase gate region, allowing for efficient carrier removal through voltage biasing methods like Fowler-Nordheim and Hot Hole effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dual-poly structure with separate control gate and floating gate is used, then programming capability is achieved, but manufacturing process complexity increases and compatibility with standard CMOS is lost
Solution Approach 1:
The patent merges the control gate and floating gate into a single polysilicon gate structure, eliminating the need for separate gate fabrication processes. This single gate serves both control and charge storage functions, achieving CMOS compatibility while maintaining programming capability through hot carrier injection mechanisms.
Solution Approach 2:
The single polysilicon gate performs multiple functions simultaneously: it acts as the control gate for device operation and as the floating gate for charge storage. This multi-functional design eliminates the need for separate dedicated structures, simplifying manufacturing while preserving memory functionality.
2Ease of operation
If conventional single-poly structure is used, then CMOS compatibility is achieved, but erasing capability is lost requiring UV light exposure
Solution Approach 1:
The patent replaces the optical erasing mechanism (UV light exposure) with an electrical field-based erasing mechanism. By applying appropriate voltage to the single polysilicon gate, the device can electrically erase stored charges through field emission or tunneling effects, eliminating the need for external UV light sources and enabling fully integrated memory operation.
3Productivity
If multiple PMOS transistors with separate gates are used, then programming functionality is achieved, but fabrication process steps increase
Solution Approach 1:
The patent combines multiple gate structures into a single polysilicon gate that serves all necessary control and storage functions. This merging reduces the number of fabrication steps, particularly eliminating sequential gate formation processes, while maintaining the ability to perform programming operations through the unified gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables multi-time programming capabilities by effectively erasing stored data without the need for ultraviolet light, improving erase efficiency and compatibility with standard CMOS processes.
Implementation Method 1
allowing for efficient carrier removal through voltage biasing methods like Fowler-Nordheim and Hot Hole effects
Implementation Method 2
allowing for efficient carrier removal through voltage biasing methods like Fowler-Nordheim and Hot Hole effects
Implementation Method 3
utilizing ion implantation and specific substrate structures to create an erase gate region
Data Source
Figure 1~2C
Figure 3A~3D
Figure 4~6
AI summary
An erasable programmable single-poly nonvolatile memory includes a substrate structure; a first PMOS transistor comprising a select gate (34), a first source/drain region (31), and a second source/drain region (32), wherein the select gate is connected to a select gate voltage, and the first source/drain region is connected to a source line voltage; a second PMOS transistor comprising the second source/drain region (32), a third source/drain region (33), and a floating gate (36), wherein the third source/drain region is connected to a bit line voltage and the first, second and third source/drain regions are constructed in an N-well region (NW); and an erase gate region (35) adjacent to the floating gate (36), wherein the erase gate region comprises an n-type source/drain region (38) connected to an erase line voltage and a P-well region (PW); wherein the N-well region (NW) and the P-well region (PW) are formed in the substrate structure.