Four-Terminal Single-Poly Memory Cell Structure for Compact Arrays
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Solution Overview
Problem
Conventional single-poly non-volatile memory cells face limitations in programming efficiency and erasing efficiency due to their complex structure and size constraints, necessitating a more efficient and compact design for improved performance.
Innovation Solution
The proposed solution involves a four-terminal memory cell structure with a select transistor, a floating gate transistor, and two capacitors, where the floating gate and assist gate regions are formed as capacitors, enhancing programming and erasing efficiency while reducing the memory cell size through a specialized structural design and bias voltage management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional single-poly non-volatile memory cell structure is used, then the memory cell can be manufactured using standard CMOS processes, but the programming efficiency and erasing efficiency are limited and the memory cell size is large
Solution Approach 1:
The patent merges the floating gate and assist gate regions to form a capacitor structure, where the floating gate serves dual purposes as both a control gate for the transistor and one terminal of the capacitor. This integration reduces the number of separate components and optimizes the use of polysilicon layers, thereby improving programming and erasing efficiency while reducing the overall memory cell area.
Solution Approach 2:
The floating gate region is designed to perform multiple functions: it acts as the control gate for the transistor channel and simultaneously serves as one terminal of the capacitor for charge storage. This multi-functionality reduces the need for separate dedicated structures, improving operational efficiency and reducing cell size.
2Productivity
If a conventional single-poly non-volatile memory cell structure is used, then the memory cell can be manufactured using standard CMOS processes, but the erasing efficiency is limited
Solution Approach 1:
The erase gate region is integrated with the transistor structure, sharing the same polysilicon layer as the floating gate. This merging allows the erase operation to utilize the existing capacitor structure formed by the floating gate and assist gate, improving erasing efficiency without requiring additional separate erase structures that would increase cell area.
Solution Approach 2:
The capacitor structure formed by the floating gate and assist gate serves as an intermediary charge storage mechanism that facilitates both programming and erasing operations. By using this intermediary structure, the patent achieves improved erasing efficiency through better charge control while maintaining a compact design.
3Productivity
If the floating gate and assist gate regions are formed as capacitors, then programming and erasing efficiency are enhanced, but the structural complexity increases
Solution Approach 1:
The patent merges the transistor gate structures with capacitor structures by having the floating gate and assist gate regions serve dual purposes. The polysilicon layers formed for the transistor gates simultaneously create the capacitor terminals, reducing the need for separate capacitor fabrication steps and simplifying the overall manufacturing process despite the enhanced functionality.
Solution Approach 2:
The same polysilicon layers and doped regions are designed to perform multiple functions: forming transistor channels, creating control gates, and establishing capacitor terminals. This multi-functionality reduces structural complexity by eliminating redundant components while still achieving enhanced programming and erasing efficiency through the capacitor formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances programming and erasing efficiency and reduces the memory cell size, enabling more efficient operations and easier integration in memory arrays with improved performance and compactness.
Implementation Method 1
The storage state of the memory cell is determined according to the number of charges stored in the floating gate of the floating gate transistor
Implementation Method 2
the first doped region, the first gate structure and the second doped region are collaboratively formed as a first capacitor, and the second doped region, the second gate structure and the third doped region are collaboratively formed as a second capacitor
Data Source
AI summary
An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily.