Single-Poly Memory Cell With Interdigitated Polysilicon Capacitor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional single-poly non-volatile memory cells face challenges in device density and manufacturing costs due to the need for extra processing steps and potential junction breakdown, with metal-layer capacitors experiencing data retention issues in advanced CMOS processes due to low-k dielectrics.
Innovation Solution
A non-volatile memory cell design utilizing a polysilicon fringe capacitor with interdigitated finger extensions for capacitive coupling between the floating gate and control gate, coupled to programming and erase lines through tunneling devices, allowing for efficient programming and erasure without relying on metal-layer capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a metal-layer capacitor is used for the control gate in single-poly non-volatile memory cells, then device density can be improved, but data retention reliability deteriorates due to low-k dielectric leakage in advanced CMOS processes
Solution Approach 1:
The patent changes the dielectric material parameter from low-k to high-k material, fundamentally altering the electrical properties of the capacitor insulator. This parameter change eliminates leakage current while preserving the high-density interdigitated finger structure, resolving the contradiction between density and retention reliability
2Area of moving object
If a trench MIM capacitor is used to implement the control gate to increase density, then device density improves, but manufacturing complexity and costs increase due to extra processing steps
Solution Approach 1:
The patent merges the control gate capacitor fabrication with the existing single-poly CMOS process flow. The interdigitated finger extensions are formed using the same polysilicon layer and processing steps as the transistor gates, eliminating the need for separate trench MIM capacitor processing while achieving high device density
3Ease of manufacture
If a buried diffusion region is used to form the control gate in single-poly memory cells, then compatibility with CMOS manufacturing is maintained, but device density decreases due to occupied die area
Solution Approach 1:
The patent transitions from a planar buried diffusion structure to a three-dimensional interdigitated finger structure. By extending the polysilicon control gate into vertical finger extensions that interdigitate with floating gate fingers, the design utilizes the third dimension to achieve high capacitance coupling without occupying additional die area, thereby increasing device density while maintaining CMOS compatibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances device density and reduces manufacturing costs while ensuring long-term data retention by leveraging high-k dielectrics compatible with CMOS processes, preventing leakage and junction breakdown.
Implementation Method 1
the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate capacitively coupling through interdigitated finger extensions
Implementation Method 2
lowering a potential of the erase line such that electrons tunnel from the erase line into the floating gate so as to program the non-volatile memory cell
Implementation Method 3
In less dense semiconductor processes, a higher-k dielectric is used to insulate the upper metal layers that inhibits leakage between the anode and cathode
Data Source
AI summary
A non-volatile memory cell includes: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a poly-silicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having finger extensions, the finger extensions from the floating gate interdigitating with the finger extensions from the control gate; anda programming line coupled to the control gate.