Single Poly Non-Volatile Memory Device Area Reduction
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Solution Overview
Problem
Conventional single poly non-volatile memory devices have inefficiencies in erase operations due to separate tunneling and sensing transistor structures, which increase memory cell area and reduce erase efficiency.
Innovation Solution
A single poly non-volatile memory device design where a selection transistor, sensing transistor, and control gate are disposed in separate wells, with the control gate connected to the sensing transistor, forming a floating gate, and doping layers are used to improve operation efficiency and reduce area by sharing drain and source areas, allowing for efficient program and erase operations without high voltage processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a separate tunneling area and sensing transistor structure is used, then the memory cell area increases, but the erase operation efficiency decreases
Solution Approach 1:
The patent merges the tunneling area and sensing transistor into a single integrated structure. The sensing transistor is positioned such that its channel region directly overlaps with the tunneling area, eliminating the need for separate structures. This integration improves erase operation efficiency by reducing the distance electrons must travel while maintaining a compact memory cell area.
Solution Approach 2:
The patent utilizes vertical stacking to arrange components in three dimensions. The control gate is positioned above the sensing transistor channel, which is above the tunneling area, creating a vertical architecture. This dimensional arrangement increases functional density without proportionally increasing the planar area, resolving the contradiction between area and efficiency.
2Device complexity
If the sensing transistor is disposed at the periphery of the source electrode, then the structure is simplified, but the substantial tunneling area reduces due to depletion area
Solution Approach 1:
The patent applies local quality by creating a heavily doped n-type region specifically at the interface between the source electrode and tunneling area. This localized doping modification reduces the depletion area effect at this critical location, maintaining a large substantial tunneling area while keeping the overall structure simple with the sensing transistor at the periphery.
3Ease of manufacture
If conventional single poly structure is used with separate tunneling and sensing areas, then manufacturing is simplified, but production time increases due to additional high voltage processes
Solution Approach 1:
The patent extracts and eliminates the high voltage process step from the manufacturing sequence. By designing the single poly structure to function as both tunneling and sensing regions, the patent removes the need for separate high voltage element formation processes, thereby simplifying the manufacturing process and reducing production time while maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances erase efficiency, reduces memory cell area, and simplifies production by eliminating the need for high voltage processes, thereby improving operational margins and data retention.
Implementation Method 1
a control gate formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor
Data Source
AI summary
A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.