Single-Poly Nonvolatile Memory Fabrication via Gate Oxide Segmentation
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Solution Overview
Problem
Conventional single-poly nonvolatile memories are limited to one-time programming (OTP) as they lack the ability to erase stored data, making them unsuitable for multi-times programming (MTP) applications, and their fabrication process is not compatible with standard CMOS manufacturing due to separate production of floating and control gates.
Innovation Solution
A method for fabricating an erasable programmable single-poly nonvolatile memory involves forming a gate oxide layer with distinct thickness portions, where one portion is injected with carriers during programming and another is ejected during erasing, allowing for the use of polysilicon gates and standard CMOS manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional programmable dual-poly nonvolatile memory is used, then data storage capability is achieved, but the fabrication process requires separate production of floating gate and control gate, making it incompatible with standard CMOS manufacturing process
Solution Approach 1:
The patent merges the floating gate and control gate into a single polysilicon gate structure. The gate oxide layer is divided into a first portion (over the channel) and a second portion (over the drain), both covered by the same polysilicon gate. This integration eliminates the need for separate floating gate and control gate fabrication processes, making the memory compatible with standard CMOS manufacturing while retaining the ability to store data through carrier injection into the gate oxide.
2Adaptability or versatility
If a conventional programmable single-poly nonvolatile memory is used, then compatibility with standard CMOS process is achieved, but the memory is limited to one-time programming (OTP) as it lacks the ability to erase stored data
Solution Approach 1:
The gate oxide layer is segmented into two distinct portions: a first portion over the channel region and a second portion over the drain region. This segmentation enables different functions - the first portion allows carrier injection for programming, while the second portion enables carrier ejection for erasing. By dividing the gate oxide into functionally distinct regions, the memory achieves both OTP and erase capabilities, enabling multi-times programming while maintaining CMOS compatibility.
Solution Approach 2:
The patent utilizes changes in voltage parameters to achieve different memory operations. By applying specific voltage combinations to the source, drain, and polysilicon gate, carriers can be injected into the gate oxide for programming or ejected from the gate oxide for erasing. The ability to dynamically change voltage parameters enables reversible data storage states, transforming the memory from OTP to multi-times programmable.
3Ease of manufacture
If the gate oxide layer has uniform thickness, then fabrication is simplified, but the memory cannot distinguish between programming and erasing operations
Solution Approach 1:
The gate oxide layer exhibits local quality variations with different thicknesses in different regions. The first portion over the channel has a different thickness than the second portion over the drain. This local thickness differentiation enables the memory to perform both programming and erasing operations using the same polysilicon gate structure. The thinner region facilitates carrier ejection for erasing, while the thicker region allows carrier injection for programming, thus achieving reversible data storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables multi-times programming capability by reducing the erase line voltage, thus allowing for reversible data storage states without compromising compatibility with standard CMOS processes.
Implementation Method 1
the first portion of the gate oxide layer are injected by a plurality of carriers during a programmed state; defining a second portion of the gate oxide layer, wherein the second portion of the gate oxide layer are ejected by the carriers during an erase state
Data Source
AI summary
The present invention provides a method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covering a surface of the first area, wherein the second gate oxide layer extends to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covering the first and the second gate oxide layers; and defining a second type doped region in the DDD region and defining first type doped regions in the second type well region.