Single-Poly Memory Layout Optimizing Conductor Edge for Leakage Reduction
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Solution Overview
Problem
Current single-poly non-volatile memory devices face challenges in achieving high memory density and programming speed due to high leakage currents at isolation structure corners and limited coupling efficiency of capacitors, making them less efficient compared to double-poly devices.
Innovation Solution
The design includes a semiconductor substrate with isolation structures, doped wells, and conductors that form transistors and capacitors, where the conductors' edges are optimized to reduce corner leakage and increase coupling efficiency by not extending beyond the doped wells, allowing for improved layout and reduced corner leakage, enabling higher programming speed and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conductor extends beyond the doped well to maximize capacitor coverage, then capacitor coupling efficiency is improved, but leakage current at isolation structure corners increases
Solution Approach 1:
The conductor is positioned to overlap with the doped well region but deliberately stops before extending beyond the isolation structure corners. This local optimization ensures the conductor maintains high coupling efficiency with the capacitor while avoiding the harmful corner regions where leakage current occurs, thus resolving the contradiction between coupling efficiency and leakage reduction
2Device complexity
If one word line controls two bit lines (conventional layout), then device complexity is reduced, but memory density and programming speed are limited
Solution Approach 1:
The memory array is segmented into four distinct memory cells per word line, with each cell having its own dedicated bit line. This segmentation allows one word line to simultaneously control four bit lines, thereby quadrupling the programming speed compared to conventional layouts while maintaining manageable device complexity through systematic arrangement
3Productivity
If double-poly structure is used to achieve high memory density, then memory density is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The invention changes the material parameter from double-poly to single-poly structure, achieving high memory density through optimized conductor geometry and layout arrangement rather than through additional material layers. This parameter change simplifies the manufacturing process while maintaining high density performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces leakage currents, enhances capacitor coupling efficiency, lowers operating voltage, and increases memory density by allowing one word line to control four bit lines, thereby improving device performance and programming speed.
Implementation Method 1
two first ion doped regions (222, 224) and a second ion doped region (232)... The second ion doped region (232) and the capacitor portion (G2) of the conductor cooperatively constitute a capacitor
Data Source
AI summary
A non-volatile memory cell includes a semiconductor substrate with isolation structures formed therein and thereby transistor region and capacitor region are defined therein. A conductor is disposed over the isolation structures, the transistor region and a first-type doped well disposed in the capacitor region. The conductor includes a capacitor portion disposed over the first-type doped well, a transistor portion disposed over the transistor region, a first edge disposed over the isolation structure at a side of the transistor region, and an opposite second edge disposed over the first-type doped well. Two first ion doped wells are disposed in the transistor region and respectively at two sides of the transistor portion, and constitutes a transistor with the transistor portion. A second ion doped region is disposed in the capacitor region excluding the conductor and constitutes a capacitor with the capacitor portion.