Single-Poly Non-Volatile Memory Cell With Metal Layer Capacitor
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Solution Overview
Problem
Conventional single-poly non-volatile memory cells face challenges in device density and manufacturing costs due to the need for buried diffusion regions and additional processing steps for trench MIM capacitors, which also lead to junction breakdown.
Innovation Solution
A non-volatile memory cell design utilizing a metal-layer capacitor with fringe capacitance, where the control gate is formed using existing semiconductor metal routing layers, eliminating the need for buried diffusion regions and additional processing steps, and enhancing capacitance through multiple metal layers and fringe capacitance junctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a buried diffusion region is used to form the control gate in single-poly non-volatile memory cells, then compatibility with CMOS manufacturing processes is achieved, but device density decreases and manufacturing costs increase
Solution Approach 1:
The invention merges the control gate function with existing metal routing layers and capacitor structures already present in CMOS processes. By utilizing the interlayer dielectric and metal layers that are already formed during standard CMOS manufacturing, the control gate is created as an integrated structure rather than a separate component, thereby maintaining CMOS compatibility while reducing overall device area and improving density.
Solution Approach 2:
The existing metal routing layers and capacitor structures in CMOS processes are made multi-functional by serving dual purposes: their original routing/capacitor function plus the additional function of forming the control gate. This eliminates the need for dedicated control gate structures and reduces the area required for each memory cell.
2Area of stationary object
If a trench MIM capacitor is used to implement the control gate to increase device density, then device density improves, but manufacturing costs increase due to extra processing steps
Solution Approach 1:
The invention combines the control gate formation with existing metal layer and interlayer dielectric structures that are already part of the CMOS process flow. By merging these functions into a single integrated structure formed during standard processing steps, the need for additional trench MIM capacitor fabrication steps is eliminated, reducing manufacturing complexity and cost while achieving high device density.
3Area of stationary object
If a trench MIM capacitor is used to implement the control gate to increase device density, then device density improves, but junction breakdown increases
Solution Approach 1:
The invention merges the control gate with existing metal and dielectric structures, eliminating the need for deep trench formations that create high-stress junctions. The integrated structure uses standard metal-dielectric interfaces that are inherently more reliable and less prone to breakdown, while still achieving high device density through efficient space utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design increases device density, reduces manufacturing costs, and minimizes junction breakdown while maintaining compatibility with CMOS semiconductor processes, achieving efficient programming and erasing of memory cells with enhanced capacitance.
Implementation Method 1
charging the metal layer capacitor to a positive programming voltage such that the voltage coupled from the metal layer capacitor through a fringe capacitance junction to the floating gate to program the non-volatile memory cell
Data Source
AI summary
A non-volatile memory cell includes a floating gate transistor having a floating gate coupled to a metal layer capacitor defined in one or more metal layers. Within each metal layer, the metal layer capacitor includes a first plate coupled to the floating gate and a second plate separated from the first plate by a fringe capacitance junction.