Single-Poly Nonvolatile Memory With Segmented Gate Oxide
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Solution Overview
Problem
Existing nonvolatile memory technologies, such as programmable dual-poly and single-poly memories, face challenges in multi-times programming due to the inability to erase stored data efficiently, as they rely on one-time programming methods like ultraviolet light exposure, which limits their reprogrammability and compatibility with standard CMOS manufacturing processes.
Innovation Solution
An erasable programmable single-poly nonvolatile memory design is introduced, featuring a floating gate transistor with a gate oxide layer and an erase gate region, where the floating gate is adjacent to the erase gate, and the gate oxide layer has varying thicknesses, enabling efficient carrier removal through a tunneling capacitor structure and optimized well region doping for improved erase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a programmable dual-poly nonvolatile memory is used to achieve nonvolatile storage functionality, then the storage capability is improved, but the manufacturing process complexity increases and compatibility with standard CMOS manufacturing process deteriorates
Solution Approach 1:
The patent merges the control gate and floating gate into a single polysilicon gate structure, eliminating the need for separate poly silicon layers. This single-gate transistor design integrates the programming and erasing functions within one gate structure, making the manufacturing process compatible with standard CMOS processes while maintaining nonvolatile storage capability through hot carrier injection and tunneling mechanisms.
Solution Approach 2:
The single polysilicon gate serves multiple functions: it acts as both the control gate for device operation and the floating gate for data storage. The gate structure can perform programming through hot carrier injection, erasing through tunneling, and read operations, replacing the need for separate control and floating gates in dual-poly designs.
2Ease of manufacture
If a conventional programmable single-poly nonvolatile memory is used to simplify manufacturing process, then the ease of manufacture is improved, but the ability to erase stored data efficiently deteriorates
Solution Approach 1:
The patent segments the gate oxide layer into two distinct regions: a first region with greater thickness for data storage and a second region with lesser thickness for data erasing. This segmentation allows different physical mechanisms to operate in different regions - hot carrier injection for programming in the thicker region and tunneling for erasing in the thinner region - enabling efficient multi-times programming while maintaining CMOS compatibility.
Solution Approach 2:
The gate oxide layer exhibits local quality variations with different thicknesses in different regions. The first region has increased thickness to facilitate hot carrier injection and data storage, while the second region has reduced thickness to enable efficient tunneling for data erasing. This local differentiation of physical properties allows the single-poly structure to achieve erasable functionality.
3Device complexity
If a single gate structure is used to reduce device complexity, then the device complexity is reduced, but the functionality for both programming and erasing operations deteriorates
Solution Approach 1:
The patent combines multiple gate functions into a single polysilicon gate structure that can perform both programming and erasing operations. The single gate controls the channel for read operations, stores data through hot carrier injection, and enables erasing through tunneling, replacing the need for separate control gates and floating gates while maintaining full functionality.
Solution Approach 2:
The patent utilizes parameter changes in the gate oxide layer thickness to enable different operational modes. By varying the oxide thickness locally (thicker for storage, thinner for erasing), the single gate structure achieves multiple functions - programming via hot carrier injection in the thicker region and erasing via tunneling in the thinner region - without increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for multi-times programming capability by efficiently removing stored carriers, enhancing erase efficiency, and maintaining compatibility with standard CMOS manufacturing processes, thus overcoming the limitations of one-time programming memories.
Implementation Method 1
enabling efficient carrier removal through a tunneling capacitor structure
Implementation Method 2
the hot carriers (e.g. hot electrons) are attracted by the control voltage on the control gate 12 and injected into the floating gate 14
Data Source
AI summary
An erasable programmable single-poly nonvolatile memory includes a substrate structure; a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region, wherein the channel region is formed in a N-well region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region and the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region. The N-well and P-well region are formed in the substrate structure. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.