Single Poly Multi-Bit Non-Volatile Memory Device
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Solution Overview
Problem
Conventional non-volatile semiconductor memory devices with a double poly process are incompatible with CMOS techniques and can only store one bit of data, limiting their density and requiring special fabrication processes.
Innovation Solution
A non-volatile memory device with a single polysilicon gate layer, featuring two floating gates on either side of a control gate, allowing for two-bit storage and compatibility with CMOS processes, using channel hot electron techniques for programming and UV radiation or Band-To-Band-Hot-Hole Injection for erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a double poly process is used to form both floating gate and control gate from polysilicon layers, then the device can store one bit of data, but the fabrication becomes incompatible with conventional CMOS techniques and requires special processes
Solution Approach 1:
The patent segments the gate structure into three distinct components: a control gate and two separate floating gates positioned on either side. This segmentation allows each gate to be independently formed using single poly deposition, eliminating the need for double poly processes while maintaining the one-bit storage capability through differential voltage sensing between the two floating gates
Solution Approach 2:
The single polysilicon layer serves multiple functions by forming both the control gate and the two floating gates. This multi-functional use of a single poly layer maintains compatibility with conventional CMOS single poly processes while achieving the desired one-bit storage functionality through the unique three-gate configuration
2Ease of manufacture
If a conventional floating gate device with single poly process is used, then compatibility with CMOS techniques is achieved, but the device can only store one bit of data limiting density
Solution Approach 1:
The patent transitions from a conventional single floating gate structure to a three-gate structure with two floating gates positioned laterally on either side of the control gate. This dimensional arrangement allows the device to store one bit of data per gate pair, effectively doubling the storage capacity while maintaining single poly process compatibility and standard CMOS fabrication
3Reliability
If double poly process is used for floating gate and control gate formation, then one bit storage is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the formation of the control gate and both floating gates into a single polysilicon deposition step. By combining what would traditionally require separate poly deposition steps into one unified process, the invention reduces fabrication complexity and manufacturing cost while maintaining the one-bit storage functionality through the innovative three-gate configuration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables higher density, reduced manufacturing costs, and compatibility with conventional CMOS processing, allowing for increased capacity and decreased footprint while maintaining data storage efficiency.
Implementation Method 1
A dielectric layer 110 is then formed over the substrate between diffusion regions 104 and 106. This dielectric layer is often a silicon dioxide (SiO2) dielectric layer and can be referred to as the tunnel oxide layer.
Implementation Method 2
If the electrons have enough energy to overcome the barrier height of the dielectric layer, then these carriers can be injected through the dielectric layer.
Implementation Method 3
The voltage applied to control gate 116 will couple with floating gate 112 to create the field component necessary to attract carriers in channel region 108 to floating gate 112.
Implementation Method 4
using channel hot electron techniques for programming
Implementation Method 5
UV radiation can be used to erase the device
Implementation Method 6
Band-To-Band-Hot-Hole Injection can be used to erase the device
Data Source
AI summary
A non-volatile memory device comprises a substrate with a dielectric layer formed thereon. A control gate is formed on the dielectric layer, as are two floating gates, one on either side of the control gate. Accordingly, the non-volatile memory device can be constructed using a single poly process that is compatible with conventional CMOS processes. In addition, the device can store two bits of data, one in each floating gate. The device can comprises two diffusion regions formed in the substrate, one near each floating gate, or four diffusion regions, one near each edge of each floating gate.