Single-Poly NVM Cell Asymmetric LDD Structure
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Solution Overview
Problem
Existing single-poly nonvolatile memory (NVM) devices face challenges in achieving low voltage operation, low power consumption, and high program performance, particularly in maintaining data retention and reducing defect-induced band-to-band tunneling disturbances.
Innovation Solution
The proposed single-poly NVM cell structure includes a semiconductor substrate with an ion well, a select transistor, and a floating gate transistor, where a silicide block layer covers the floating gate, and a contact etch stop layer is used to isolate the floating gate from the inter-layer dielectric, reducing electron trapping and enhancing data retention. The structure features asymmetric lightly doped drain configurations and self-aligned salicide layers to optimize programming efficiency and reduce voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional single-poly NVM structure is used, then the device is compatible with regular CMOS process, but the program performance is insufficient and power consumption is high
Solution Approach 1:
The NVM cell is segmented into distinct functional regions with asymmetric LDD configurations - the select transistor has LDD regions at both source and drain, while the floating gate transistor has LDD regions only at the source side. This segmentation allows optimized charge injection paths that improve program performance while reducing the voltage and power required for programming operations.
Solution Approach 2:
The patent applies local quality by creating asymmetric doping regions - specifically, the floating gate transistor has lightly doped drain regions only on the source side, while the drain side remains heavily doped. This localized modification of doping characteristics enhances the tunneling efficiency for programming while minimizing power consumption during write operations.
2Reliability
If the gate oxide layer is made thicker to improve data retention, then data retention is improved, but higher program voltages are required
Solution Approach 1:
The patent changes the structural parameters of the transistor by introducing asymmetric LDD configurations and salicide layers. These parameter changes modify the electric field distribution and charge injection characteristics, enabling effective programming of thicker gate oxide layers (up to 160 angstroms or more) without requiring excessively high program voltages, thus maintaining data retention while controlling stress.
3Ease of manufacture
If standard NVM structure is used, then manufacturing is straightforward, but defect-induced band-to-band tunneling disturbances occur
Solution Approach 1:
The patent converts the potential harm of defects into a benefit by designing asymmetric LDD structures that create controlled electric field distributions. The lightly doped regions on the source side of the floating gate transistor are specifically positioned to enhance desired tunneling while the asymmetric configuration naturally suppresses defect-induced band-to-band tunneling disturbances, transforming a vulnerability into a protective feature.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances program efficiency, reduces power consumption, and improves data retention by minimizing defect-induced disturbances, while allowing for lower program voltages, especially for memory cells with thicker gate oxide layers.
Implementation Method 1
a floating gate oxide layer between the floating gate and the semiconductor substrate, a select gate oxide layer between the select gate and the semiconductor substrate
Implementation Method 2
a source doping region in the ion well, a first lightly doped drain (LDD) region merged with the source doping region, a commonly-shared doping region spaced apart from the source doping region, and a second LDD region merged with the commonly-shared doping region
Data Source
AI summary
A single-poly NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor. The select transistor includes a select gate, a select gate oxide layer, a source doping region, a first LDD region merged with the source doping region, a commonly-shared doping region, and a second LDD region merged with the commonly-shared doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, the commonly-shared doping region, a third LDD region merged with the commonly-shared doping region, and a drain doping region. A drain-side extension modified region is disposed under the spacer and in proximity to the drain doping region.