Single Poly NVM Cell Design for CMOS Compatibility
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Solution Overview
Problem
Existing nonvolatile memory (NVM) devices face challenges in being used as system-on-chip (SOC) embedded memory due to their double poly process, which differs from the standard CMOS process, leading to misalignment issues and reduced fabrication yield in single poly NVM devices.
Innovation Solution
A single poly NVM cell design with a P-channel floating gate transistor and a P-channel read selection transistor, where the floating gate extends over the active regions, and an interconnection line connects N-type well regions to the P-type source region, allowing for programming and erasing without negative bias voltages and word line decoders, simplifying the memory cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a double poly process is used to fabricate NVM devices, then the memory device functionality is achieved, but the fabrication process becomes complex and incompatible with standard CMOS processes
Solution Approach 1:
The patent changes the material parameter from double poly to single poly, making the NVM device compatible with standard CMOS fabrication processes while maintaining the required memory functionality through modified device structure and operation methods
2Reliability
If a stacked gate structure with floating gate and control gate electrode is used, then the NVM device functionality is achieved, but the fabrication yield decreases due to misalignment issues
Solution Approach 1:
The patent extracts and eliminates the floating gate electrode from the stacked gate structure, retaining only the control gate electrode. This simplification removes the misalignment problem between floating gate and control gate while maintaining NVM functionality through alternative mechanisms
3Reliability
If negative bias voltages and word line decoders are used in memory cell operation, then the memory cell functionality is achieved, but the memory cell area increases
Solution Approach 1:
The patent extracts and eliminates the word line decoder circuit from the memory cell structure. The simplified operation method directly controls the memory cell without requiring external decoding logic, thereby reducing the overall memory cell area while maintaining full functionality
Solution Approach 2:
The memory cell structure is designed to be self-sufficient, with the control gate electrode and associated circuits directly integrated into the cell. This eliminates the need for separate word line decoder circuits that would otherwise be required to control the cell, reducing area while maintaining functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the fabrication yield and simplifies the memory cell area by eliminating the need for negative bias voltages and word line decoders, enabling efficient programming, erasing, and reading operations in single poly NVM devices.
Implementation Method 1
a P-channel floating gate transistor including a floating gate disposed in the first active region
Implementation Method 2
applying a positive program voltage and a ground voltage to the array control gate line and the tunnel/source line, respectively
Data Source
AI summary
A single poly NVM cell includes a first N-type well region and a second N-type well region spaced apart from each other by a P-type semiconductor layer, a first active region and a second active region disposed in the first N-type well region and the second N-type well region, respectively, a P-channel floating gate transistor including a floating gate disposed in the first active region, a P-type drain region disposed in the first active region, and a P-type junction region disposed in the first active region, wherein the floating gate extends to over the second active region, a P-channel read selection transistor including a read selection gate electrode disposed in the first active region, the P-type junction region disposed in the first active region, and a P-type source region disposed in the first active region, and an interconnection line connecting the first N-type well region to the P-type source region of the P-channel read selection transistor.