Single-Poly Floating Gate NVM Cell With Contact Control Gate

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Solution Overview

Problem

Existing single poly floating gate EEPROM technologies face issues such as high voltage requirements for erase and program operations, significant area consumption, and increased bit cell size due to silicon protection masks, leading to inefficiencies and higher costs.

Innovation Solution

A nonvolatile memory cell design utilizing a silicide protection dielectric layer as the capacitive coupling dielectric between the control and floating gates, with control gate contacts positioned outside the active region, and a field plate metal as a control gate contact to reduce voltage requirements and bit cell area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a single poly floating gate EEPROM is used with integrated CMOS polysilicon, then manufacturing cost is reduced, but high voltage is required for erase and program operations

Engineering Contradiction:

Improvemanufacturing costVSAvoidvoltage requirement

Core Design Contradiction:

Ease of manufactureVSUse of energy by moving object

Solution Approach 1:

A nitride layer is introduced as an intermediary between the floating gate and the tunnel oxide. This nitride layer enables Fowler-Nordheim tunneling at lower voltages by providing a suitable barrier height and thickness, thereby reducing the high voltage requirement while maintaining the integrated CMOS polysilicon structure

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The tunnel oxide thickness is optimized and adjusted to work in conjunction with the nitride layer. By changing the oxide thickness parameter, the tunneling conditions are improved, allowing effective program and erase operations at reduced voltages while keeping the manufacturing process simple

Inventive Principle:

Principle #35Parameter changes

2Reliability

If a silicon protection mask is used to isolate the floating gate from borderless nitride layer, then charged loss is prevented, but bit cell size increases

Engineering Contradiction:

Improveretention propertiesVSAvoidbit cell size

Core Design Contradiction:

ReliabilityVSArea of moving object

Solution Approach 1:

The silicon protection mask is completely removed from the structure. Instead, the floating gate is isolated from the borderless nitride layer through proper spatial arrangement and the use of the nitride layer itself as the isolation mechanism, eliminating the need for additional protection masks and reducing bit cell area

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The nitride layer serves multiple functions simultaneously: it acts as the tunnel barrier for Fowler-Nordheim tunneling, provides isolation between the floating gate and surrounding structures, and eliminates the need for separate protection masks. This multi-functionality reduces overall device complexity and area

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Use of energy by moving object

If hot electrons or hot hole injection is used to lower program and erase voltages, then voltage requirement is reduced, but power consumption increases

Engineering Contradiction:

Improvevoltage requirementVSAvoidpower consumption

Core Design Contradiction:

Use of energy by moving objectVSLoss of energy

Solution Approach 1:

The hot electron/hole injection mechanism is replaced with Fowler-Nordheim tunneling through the nitride layer. This quantum mechanical tunneling process is more efficient and requires less energy dissipation, thereby reducing power consumption while achieving lower operating voltages

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Area of moving object

If ad hoc process steps are introduced to reduce bit cell area, then area consumption is reduced, but manufacturing complexity increases

Engineering Contradiction:

Improvebit cell sizeVSAvoidprocess steps

Core Design Contradiction:

Area of moving objectVSDevice complexity

Solution Approach 1:

The nitride layer deposition is merged with the existing CMOS fabrication process flow. The same polysilicon layer that forms the CMOS gates is also used to form the floating gate, and the nitride layer is deposited using standard PECVD equipment already present in the CMOS line, eliminating the need for ad hoc process steps

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces power consumption, minimizes bit cell size, and enhances retention properties by lowering program and erase voltages, while maintaining effective capacitive coupling and reducing the number of cycles before program window narrowing occurs.

Implementation Method 1

utilize a silicide protection dielectric layer as the capacitive coupling dielectric of the control gate and floating gate of the floating gate transistor

Methodology Applied

Scientific EffectCapacitive coupling: Capacitance

Implementation Method 2

a dielectric layer interposed between the control gate and the floating gate

Methodology Applied

Scientific EffectDielectric property: Dielectric

Data Source

PatentUS20250351346A1Non-volatile memory cell with single poly floating gate and contact control gate

Publication Date: 2025.11.13 STMICROELECTRONICS INT NV

AI summary

A cost-effective solution to implement a non-volatile memory cell based on floating gate transistor including a floating gate that overlies an active region and a field region of a semiconductor substrate: Single Poly Floating Gate NVM bitcell. The control gate terminal is implemented with contact plug/s (Contact Control Gate) or metal field plate separated by the floating gate using commonly present in CMOS process SIPROT stack (oxide(s) and nitride(s)).