Single-Poly Non-Volatile Memory Cell Structure

The patent merges the non-volatile memory cell structure with the logic transistor structure by sharing the control gate and using the same poly-silicon layer for both the memory floating gate and the logic transistor gate. This integration allows the memory to be manufactured using the existing logic process without requiring additional masks or process steps, thereby reducing manufacturing complexity while maintaining compatibility with standard CMOS logic processes

The control gate serves dual functions: it acts as the gate for the logic transistor and simultaneously forms the floating gate for the non-volatile memory cell. This multi-functionality enables a single structure to perform both logic operation and memory storage functions, eliminating the need for separate memory fabrication processes and reducing overall device complexity

The patent combines the memory cell fabrication with the logic transistor fabrication into a single unified process. By using the same poly-silicon deposition and patterning steps for both the logic gate and the memory floating gate, the invention eliminates redundant manufacturing steps, reduces material consumption, and lowers overall manufacturing costs while ensuring reliable memory functionality

The existing logic process infrastructure and existing transistors are utilized to provide the necessary components for memory fabrication. The logic transistors themselves serve as part of the memory cell structure, and the existing process capabilities are leveraged to create the memory functionality without requiring additional specialized equipment or processes, thereby reducing manufacturing costs