Single-Poly NVM Bit Cell Layout for Smaller CMOS Footprint
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Solution Overview
Problem
Conventional non-volatile memory (NVM) cells on CMOS integrated circuits require separate control and floating gate transistors, leading to a large footprint and significant area consumption on semiconductor dies.
Innovation Solution
A single-poly NVM bit cell design is implemented, where the control gate and floating gate are integrated with a state transistor, sharing a common polysilicon layer, and separated by an isolation trench, reducing the overall footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate control gate and floating gate transistors are used, then the NVM cell can perform programming and erasing operations, but the footprint area increases significantly
Solution Approach 1:
The patent combines the control gate and floating gate transistors into a single integrated structure where the control gate is formed directly over the floating gate. This merging eliminates the need for separate transistor structures while maintaining the ability to perform both programming and erasing operations through the shared gate structure.
Solution Approach 2:
The integrated control gate-floatling gate structure serves multiple functions simultaneously: it acts as both the control mechanism for charge injection during programming and the control mechanism for charge removal during erasing. The shared polysilicon layer and gate structure enable both operations without requiring separate dedicated transistors.
2Ease of manufacture
If separate control gate and floating gate transistors are used, then the NVM cell can be fabricated using conventional CMOS processes, but the area consumption on semiconductor dies increases
Solution Approach 1:
The patent merges the control gate and floating gate into a single integrated transistor structure that can be fabricated using standard single-poly CMOS processes. The shared polysilicon layer is formed in a single deposition and patterning step, maintaining compatibility with conventional manufacturing while reducing the total area required for each NVM cell.
3Area of stationary object
If the footprint of NVM cells is reduced, then the area consumption decreases, but the isolation and separation of transistors becomes more difficult
Solution Approach 1:
By merging the control gate and floating gate into a single integrated structure, the patent reduces the number of discrete transistor components that require isolation. The shared gate structure eliminates the need for complex isolation schemes between separate control and floating gate transistors, simplifying the overall device architecture while maintaining compact footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces the area consumption on semiconductor dies while maintaining efficient programming, erasing, and reading operations through optimized voltage application and shared polysilicon layer capacitance.
Implementation Method 1
The shared polysilicon layer functions as a floating terminal of the control gate and a floating-gate terminal of the state transistor, with a shared gate capacitance formed by a tunnel oxide layer between the first n-well and the shared polysilicon layer.
Implementation Method 2
with a shared gate capacitance formed by a tunnel oxide layer between the first n-well and the shared polysilicon layer
Data Source
AI summary
A non-volatile memory (NVM) bit cell is disclosed. The NVM bit cell includes a first well region and a second well region. The NVM bit cell also includes an isolation trench between the first well region and the second well region. The isolation trench has a trench depth that is greater than a well depth of the first well region and the second well region. The NVM bit cell further includes a control gate formed in the first well region. In addition, the NVM bit cell includes a state transistor formed in the second well region. The state transistor has a floating-gate terminal coupled to a floating terminal of the control gate. The NVM bit cell also includes an access transistor formed in the second well region and coupled in series with the state transistor.