Single-Poly Non-Volatile Memory Device Low-Voltage Operation
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Solution Overview
Problem
Conventional single-poly non-volatile memory devices face challenges in miniaturization due to increased operational voltage requirements and insufficient tunnel oxide thickness, leading to reliability issues and incompatibility with advanced logic processes, particularly at the 90 nm technology node.
Innovation Solution
A double-channel single-poly non-volatile memory device with a method for low-voltage programming, reading, and erasing operations, utilizing an ion well, source and drain doping regions, and a channel region with a gate dielectric layer and dielectric spacer containing a floating charge trapping medium, allowing for the generation and trapping of hot electrons and holes to manage threshold voltage and data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-poly non-volatile memory structure is used, then charge storage capability is achieved, but operational voltage requirement increases and tunnel oxide thickness becomes insufficient for miniaturization
Solution Approach 1:
The invention divides the memory device into two independent channels: a gate channel for reading operations and a spacer channel for programming and erasing operations. This segmentation allows each channel to be optimized independently, enabling miniaturization while maintaining reliable charge retention through the spacer channel's dedicated programming mechanism
Solution Approach 2:
The invention introduces a charge trapping layer as an intermediary between the control gate and the floating gate. This charge trapping layer enables low-voltage programming by trapping charges during programming operations and releasing them during erasing operations, thereby reducing the operational voltage requirements while maintaining charge storage capability
2Reliability
If double-poly non-volatile memory is used, then non-volatile storage is achieved, but manufacturing complexity and thermal budget increase
Solution Approach 1:
The invention uses a single polysilicon gate that serves multiple functions: it acts as the control gate for both reading and programming/erasing operations. The gate channel and spacer channel share the same control gate structure, eliminating the need for separate poly gates and simplifying the manufacturing process while maintaining non-volatile storage capability
Solution Approach 2:
The invention changes the operational parameters by using low-voltage programming through the spacer channel instead of high-voltage programming. This parameter change allows the memory to achieve non-volatile storage without requiring additional thermal budget or complex manufacturing processes associated with double-poly structures
3Reliability
If conventional single-poly memory programming method is used, then data storage is achieved, but programming voltage requirement is high
Solution Approach 1:
The invention separates programming and erasing operations to occur through the spacer channel while reading operations use the gate channel. This segmentation allows programming to be performed at low voltages through the spacer channel, reducing energy consumption while maintaining reliable data storage capability
Solution Approach 2:
The charge trapping layer acts as an intermediary that enables low-voltage charge injection during programming. By trapping charges in this intermediate layer rather than directly in the floating gate, the system achieves data storage with reduced programming voltage requirements and lower energy consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient programming, reading, and erasing operations at reduced voltages, enhancing compatibility with next-generation logic processes and reducing the size of memory units while maintaining reliable charge retention and minimizing the use of oxide layers.
Implementation Method 1
hot electrons are re-directed, injected and trapped in the floating charge trapping medium due to a vertical electric field generated by the gate voltage (VG)
Implementation Method 2
carriers are drawn into the first channel from the source doping region to generate channel hot electrons (CHEs) due to ion impact ionization
Data Source
AI summary
A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a dielectric stack layer on sidewalls of the gate, a source doping region and a drain doping region. The dielectric stack layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the ion well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.