Single Polysilicon Layer Non-Volatile Memory Design
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Solution Overview
Problem
In the semiconductor industry, as devices shrink to deep sub-micron sizes, non-volatile memory devices face challenges with reduced memory cell sizes, increased fabrication costs, and reliability issues due to the short-channel effect and hot electron effects, which hinder the integration and reliability of memory devices.
Innovation Solution
A single-polysilicon layer non-volatile memory design eliminates the need for a select transistor by using a program gate, control gate, and erase gate under a floating gate separated by a tunneling dielectric layer, allowing charge injection and expulsion through different regions, and employs the Fowler-Nordheim tunneling effect for program and erase operations to reduce device size and operation voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple polysilicon layers and multiple dielectric layers are used to fabricate non-volatile memory, then the memory device can maintain data storage functionality, but the fabrication process becomes prolonged and fabrication cost increases
Solution Approach 1:
The patent merges the floating gate and control gate into a single polysilicon layer structure, where the same polysilicon layer serves both functions. This eliminates the need for separate polysilicon layers and reduces the number of fabrication steps while maintaining the essential charge storage and control functionality of traditional multi-layer structures
Solution Approach 2:
The single polysilicon layer is designed to perform multiple functions simultaneously - acting as both the floating gate for charge storage and the control gate for voltage control. This multi-functional design simplifies the device structure and reduces fabrication complexity while preserving data storage capability
2Reliability
If a select transistor is included in the memory cell structure, then the memory device can operate reliably, but the memory cell size cannot be further reduced
Solution Approach 1:
The patent extracts and eliminates the select transistor from the traditional memory cell structure. Instead of using a separate select transistor to control memory cell access, the design relies on the inherent control characteristics of the single polysilicon layer structure and the tunneling dielectric layer to achieve selective operation, thereby reducing memory cell area
Solution Approach 2:
The control functionality previously separated in the select transistor is merged into the single polysilicon layer structure itself. The polysilicon layer directly controls the tunneling effect and charge injection/extraction processes, eliminating the need for additional transistors and reducing overall cell size
3Productivity
If the line width is reduced to increase integration, then the memory device can achieve higher integration, but the short channel effect occurs causing threshold voltage drop and poor gate voltage control
Solution Approach 1:
The patent changes the operational parameters by utilizing the Fowler-Nordheim tunneling effect instead of conventional hot electron injection. This allows the device to operate effectively at smaller dimensions by controlling charge injection through quantum tunneling rather than hot carrier mechanisms, maintaining threshold voltage control at reduced line widths
Solution Approach 2:
The patent replaces the conventional hot electron injection mechanism with quantum mechanical Fowler-Nordheim tunneling. This substitution enables effective charge injection at lower voltages and smaller dimensions, overcoming the short channel effects that plague conventional approaches at deep sub-micron scales
4Productivity
If the channel size is reduced to increase integration, then the memory device can achieve higher integration, but the hot electron effect occurs adversely influencing memory operation
Solution Approach 1:
The patent converts the harmful hot electron effect into a beneficial mechanism by utilizing Fowler-Nordheim tunneling. Instead of relying on hot electron injection that causes damage at small dimensions, the design uses controlled quantum tunneling through the tunneling dielectric layer, turning the challenge of small尺寸 operation into an advantage by enabling precise charge control without hot carrier damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances memory cell reliability, reduces device size, and minimizes the short-channel effect, leading to more compact and reliable memory devices with lower power consumption and integration of memory devices without altering the conventional CMOS fabrication process.
Implementation Method 1
a program operation and an erase operation can be performed according to a Fowler-Nordheim (F-N) tunneling effect
Data Source
AI summary
A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory.