Single-Port Memory Emulating Dual-Port via Bank Segmentation
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Solution Overview
Problem
Dual-port memories are less reliable at low voltages and sensitive to failures, making them unsuitable for critical applications like automotive and medical fields, while single-port memories cannot operate simultaneously for read and write operations, limiting their performance.
Innovation Solution
A single-port memory system is designed to operate in a dual-port mode by using multiple single-port memory banks and a status register to manage read/write operations, allowing simultaneous access without halving the clock frequency, thus enhancing reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual-port memory is used to enable simultaneous read and write operations, then performance is improved, but reliability at low voltages deteriorates
Solution Approach 1:
The memory device is divided into multiple single-port memory banks (first memory bank, second memory bank, etc.) instead of using a single dual-port memory. Each memory bank can be independently accessed, allowing simultaneous read and write operations to be distributed across different banks. This segmentation approach maintains the performance benefit of simultaneous operations while using more reliable single-port memory structures.
2Adaptability or versatility
If single-port memory operates in dual-port mode by accessing in alternate clock cycles, then dual-port functionality is achieved, but maximum clock frequency is halved
Solution Approach 1:
The memory system is segmented into multiple parallel memory banks that can operate simultaneously in different clock cycles. The control logic manages address multiplexing to enable simultaneous read and write operations without halving the clock frequency, as each bank operates at full frequency independently.
Solution Approach 2:
Instead of time-multiplexing operations sequentially (one dimension), the invention uses spatial parallelism by distributing operations across multiple memory banks (adding a spatial dimension). This allows simultaneous read and write operations to occur in parallel without compromising clock frequency.
3Productivity
If two single-port memory banks are duplicated to achieve single-cycle dual-port mode, then performance is improved, but circuit area increases
Solution Approach 1:
Multiple single-port memory banks share common control logic, address multiplexing circuits, and data bus infrastructure. The control logic unit serves all memory banks universally, managing address selection and data routing for both read and write operations. This multi-functionality approach reduces the overall circuit area compared to duplicating complete dual-port memory structures.
Data Source
AI summary
A single-port memory that operates in single-cycle dual-port mode has a logical capacity of N=k·m memory words and (k+1) single-port RAM having an overall physical capacity of (k+1)·m memory words. A status register holds words identifying which RAM bank has the last data at the ith address in the RAM banks and defining k status words for valid data among the (k+1) RAM banks. Write data is written to the write address of a valid RAM bank for a write operation in the absence of RAM bank read address contention. Write data is written to the write address of a different RAM bank that has no valid data for a write operation if there is contention with the RAM bank read address RADDR of a read operation. The status register is updated to identify the RAM bank of the write operation.