Single-Port Memory Mapping for Parallel Read-Write Throughput
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Solution Overview
Problem
Dual-port memories face inefficiencies in handling non-sequential access and bias issues when used in memory systems, particularly with iterative ECC decoders, leading to reduced throughput and potential need for additional memory capacity.
Innovation Solution
Implementing a system with two single-port memories that dynamically assign logical addresses to physical locations using a logical to physical map, allowing parallel read and write operations by directing reads to one memory and writes to the other, while maintaining a table to track physical locations and adjust for bias through initial mapping and dynamic assignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual-port memory is used to handle parallel read and write operations, then throughput is improved, but device complexity and cost increase
Solution Approach 1:
The patent divides the memory system into two separate single-port memories instead of using one dual-port memory. Each single-port memory handles specific operations (read or write), eliminating the need for complex port arbitration logic while achieving parallel operation capability. This segmentation reduces device complexity and cost.
Solution Approach 2:
The patent introduces a logical-to-physical address map as an intermediary mechanism to coordinate access between the two single-port memories and the iterative decoder. This map translates logical addresses to physical locations in either memory, enabling efficient parallel read-write operations without requiring complex dual-port memory structure.
2Speed
If dual-port memory is used for iterative ECC decoding, then processing speed is improved, but memory capacity requirements increase due to bias
Solution Approach 1:
The patent implements dynamic address assignment where the logical-to-physical address map can be reconfigured during operation. The system dynamically determines which single-port memory should handle read or write operations based on the current decoding state, allowing flexible utilization of memory capacity and eliminating the static bias inherent in dual-port memory configurations.
Solution Approach 2:
The patent changes the addressing parameters by maintaining a logical-to-physical address map that maps logical addresses to physical locations in either of the two single-port memories. This parameter transformation enables the system to distribute data across both memories efficiently, reducing the total memory capacity needed compared to dual-port memory while maintaining processing speed.
3Device complexity
If single-port memory is used with sequential access, then device complexity is reduced, but throughput decreases due to wait states
Solution Approach 1:
The patent segments the memory system into two independent single-port memories, each capable of handling operations independently. This segmentation eliminates wait states because read and write operations can occur simultaneously in different memories, achieving parallel throughput while keeping each memory unit simple and maintaining low device complexity.
Data Source
AI summary
An apparatus includes a first single-port memory, a second single-port memory, and one or more control circuits in communication with the first single-port memory and in communication with the second single-port memory. The one or more control circuits are configured to initiate a read of stored data on a clock cycle from a physical location of the stored data in the first or second single-port memory and to initiate a write of fresh data on the clock cycle to whichever of the first single-port memory or the second single-port memory does not contain the physical location of the stored data.