Single-Port Memory Multi-Port Functionality via Frequency Multiplexing
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Solution Overview
Problem
Existing memory devices, such as single-port memories, can only perform either read or write operations within a clock cycle, limiting their ability to provide simultaneous multi-port functionality required in digital circuit designs for data buffering and transfer operations.
Innovation Solution
A memory device and method that utilize a single-port memory with read and write synchronization modules, a read/write signal selector, and a read out data synchronization module to synchronize signals and data between different clock frequencies, enabling simultaneous read and write operations akin to multi-port memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-port memory is used, then device complexity is reduced, but the ability to perform simultaneous read and write operations is lost
Solution Approach 1:
The patent applies dynamics by making the single-port memory dynamically switch between read and write modes at different clock cycles. The memory operates at a higher frequency (at least twice) than the external interface, allowing it to perform read and write operations in alternating half-cycles, thereby achieving simultaneous multi-port functionality through temporal multiplexing while maintaining a simple single-port structure
Solution Approach 2:
The patent implements periodic action by dividing the clock cycle into two phases: the first clock cycle is dedicated to write operations, and the second clock cycle is dedicated to read operations. This periodic alternation between write and read phases allows the single-port memory to service multiple ports over time, achieving the functional equivalence of a multi-port memory without the structural complexity
2Productivity
If a multi-port memory is used, then simultaneous read and write operations are enabled, but device complexity increases
Solution Approach 1:
The patent applies universality by making the single-port memory perform multiple functions (both read and write operations) that would traditionally require separate dedicated ports. By operating at a higher frequency and time-multiplexing the single port between read and write functions, the memory achieves multi-port functionality with a single port structure, reducing device complexity while maintaining productivity
Solution Approach 2:
The patent changes the operating frequency parameter of the memory to at least twice the external interface frequency. This parameter change enables the memory to complete both read and write operations within one external clock cycle, allowing the single-port memory to provide multi-port functionality without increasing structural complexity
3Reliability
If signal synchronization is implemented, then data integrity is maintained, but synchronization latency is introduced
Solution Approach 1:
The patent applies preliminary action by performing write operations in the first clock cycle before read operations in the second clock cycle. This ensures that data written in one cycle is fully settled and synchronized before being read in the next cycle, maintaining data integrity while minimizing latency through predictable, pre-planned operation sequencing
Data Source
AI summary
A memory device operable to provide multi-port functionality, which may comprise a single-port memory having a first operating frequency that is at least twice of a second operation frequency of a multi-port memory, a read synchronization module that synchronizes a set of read signals from the second operation frequency to the first operating frequency, a write synchronization module that synchronizes a set of write signals from the second operation frequency to the first operating frequency, a read/write signal selector that integrates a set of synchronized read signals and a set of synchronized write signals into a set of input control signals of the single-port memory, and a read out data synchronization module configured to synchronize a set of read out data from the single-port memory with the second operation frequency of the multi-port memory.