Single-Port Memory Read-Write Circuit for Same-Address Access
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Solution Overview
Problem
Conventional memory circuits incur timing and power penalties due to independent read and write operations, requiring internal nodes to reset after each cycle, even if the address remains the same, leading to inefficiencies in memory access operations.
Innovation Solution
The implementation of eviction-allocation (EVA) methodologies in memory circuitry allows for combined read and write operations at the same address in a single memory access, reducing the number of cycles needed and eliminating the need for re-decoding addresses and precharging bitlines, thereby improving performance and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If independent read and write operations are performed in conventional memory circuits, then each operation can be completed with standard reset procedures, but timing penalties and power consumption increase due to repeated resetting of internal nodes and precharging of bitlines
Solution Approach 1:
The patent combines read and write operations into a single unified operation sequence. When a write operation follows a read operation to the same address, the memory circuit performs both operations in one access cycle by maintaining the wordline activation state and avoiding intermediate reset of internal nodes. This merging eliminates the timing penalty of separate operations while ensuring both read and write completeness.
Solution Approach 2:
The patent prepares the memory circuit for combined operations by detecting when a write operation targets the same address as a previous read operation. The system preliminarily determines that internal nodes do not need resetting and that bitlines can be reused without precharging, thereby avoiding unnecessary timing delays before executing the write operation.
2Reliability
If internal nodes are reset after each read or write operation in conventional circuits, then the memory circuit returns to a known state, but power consumption increases due to repeated precharging and discharging of bitlines
Solution Approach 1:
The patent dynamically adjusts the reset and precharge behavior based on the operation sequence. When a write operation immediately follows a read operation to the same address, the system determines that internal nodes remain in a valid state and does not perform resetting or precharging. This dynamic adaptation maintains state stability when needed while eliminating unnecessary power consumption when the same address is accessed consecutively.
Solution Approach 2:
The memory circuit monitors its own operation history to detect when combined read-write operations are possible. By self-detecting that internal nodes are already in a valid state for the next operation, the system avoids unnecessary reset and precharge cycles, thereby reducing power consumption while maintaining operational reliability.
3Measurement precision
If address decoding and bitline precharging are performed for each independent memory access, then correct data access is ensured, but the number of eviction operations increases and performance decreases
Solution Approach 1:
The patent merges the address decoding and bitline precharging steps into a single operation when consecutive accesses target the same address. The system detects that the address remains valid across read and write operations, eliminating redundant decoding and precharge cycles. This merging maintains address accuracy while significantly improving eviction operation efficiency by reducing the total number of operation cycles.
Data Source
AI summary
Various implementations described herein are directed to a device having various circuitry for reading first data from a memory location in single-port memory and writing second data to the memory location in the single-port memory after reading the first data from the memory location. In some implementations, reading the first data and writing the second data to the memory location are performed in a single operation.